De Geus showed data from market research firm International Business Strategies (IBS) indicating that non-reoccurring engineering costs are growing at an alarming rate and are projected to pass $100 million per design by the 32-nm node. The cost increase is being driven by a rise in software and verification costs, according to the data.
This cost increase is making it increasingly difficult to design chips for anything other than large markets. Investing $90 million in R&D on a design requires a market opportunity of at least $400 million, according to the IBS data presented by de Geus. The global recession is accelerating these trends, according to de Geus.
On the alarming rise in verification complexity and cost, de Geus presented data from the International Technology Roadmap for Semiconductors indicating that a 675 percent increase in verification complexity is required over the next seven years.
De Geus' presentation referenced Synopsys' acquisitions over the past three years of Synplicity, Virtio Corp. and ProDesign's CHIPit business unit as evidence that Synopsys is investing in hardware-software co-verification technologies in order to facilitate system prototyping.
De Geus detailed Lynx, an automated chip development environment introduced by the company Monday. According to Synopsys (Mountain View, Calif.), Lynx combines an RTL-to-GDSII design flow with productivity-enhancing features to accelerate chip development while mitigating the risks of designing at new process nodes. A Synopsys employee joined de Geus on stage to do a demo of the new tool.
In his presentation, de Geus also highlighted other recent Synopsys product innovations, including a 2-3X speed-up in design turnaround time from the latest release of IC Compiler, advancements in the Galaxy Implementation Platform, USB 3.0 IP cores and flexible multicore processing technology in the the latest release of the PrimeTime static timing analysis tool.
Elsewhere Monday, at the ISQED conference,
Synopsys announced Yield Explorer, a new yield management tool said to expedite the discovery and mitigation of yield limiters in leading-edge integrated circuits.