PORTLAND. Ore. An IBM researcher says Moore's Law is running out of gas.
IBM Fellow Carl Anderson, who oversees physical design and tools in its server division, predicted during the recent International Symposium on Physical Design 2009 conference the end of continued exponential scaling down of the size and cost of semiconductors. The end of the era of Moore's Law, Anderson declared, is at hand.
Anderson was one of 65 semiconductor gurus speaking at the conference, which also unveiled a new method for synthesizing critical paths, a host of analog design innovations and a new twist on the annual physical design contest.
The IBM Fellow observed that like the railroad, automotive and aviation industries before it, the semiconductor industry has matured to the point that the pace of continued innovation is slowing.
"There was exponential growth in the railroad industry in the 1800s; there was exponential growth in the automobile industry in the 1930s and 1940s; and there was exponential growth in the performance of aircraft until [test pilots reached] the speed of sound. But eventually exponential growth always comes to an end," said Anderson.
A generation or two of continued exponential growth will likely continue only for leading-edge chips such as multicore microprocessors, but more designers are finding that everyday applications do not require the latest physical designs, Anderson said.
Consequently, Moore's Law--halving of the dimensions and doubling of speed of chips every 18 months--will run out of steam very soon. Only a few high-end chip makers today can even afford the exorbitant cost of next-generation research and design, much less the fabs to build them.
Anderson cited three next-generation technologies that were still on the fast track for exponential growth: optical interconnects, 3-D chips and accelerator-based processing. He predicted that rack-to-rack optical interconnects will become commonplace, with chip-to-chip optical connections on the same board coming soon. But Anderson said on-chip optical signaling remains years away.
He also predicted that stacked DRAM dies would be the first to go 3-D.
The conference's best paper award went to researcher Qunzeng Liu and Professor Sachin Sapatnekar of the University of Minnesota, The paper described their method of synthesizing a critical path during design process that could then serve as a representative for post-silicon delay prediction. The representative critical path could serve as a "canary in a coal mine" for tuning post-silicon yield enhancement, they said.
"With the increasing variability concerns and performance deviation due to the variability in advanced technologies," said Gi-Joon Nam, the conference general chair, "post-silicon analysis and optimization is attracting attention to actually measuring variability in order to improve the performance of silicon."
Nam added that the research "can be extremely useful, particularly in high-end technology nodes with significant variations."
Simulations predict less than 3 percent prediction errors when synthesizing a representative critical path (RCP). Sapatnekar's group plans to test their techniques on silicon chips to confirm the effectiveness of RCPs.