As designers approach 45 nm, the difference between ASICs and SoCs really blurs and, essentially, all chips become SoCs. At the same time, platform-based design, with the use and reuse of internal and external IP blocks, is playing a bigger and bigger role, because nobody is going to build a 50-M gate chip from scratch. In this changing environment, formal verification should be integral to these flows, but several common misconceptions may slow adoption of this critical technology.
What is indisputable though is that all today's conventional verification tools are proving insufficient as we head toward 45-nm designs; and building faster and larger compute farms and utilizing specialized hardware is not the answer. New methodologies and technology are needed, and quickly, to address the challenge.
An important weapon in the verification arsenal is formal verification. Once the province of experts with very specialized knowledge, over time the difficult parts have been pushed under the hood and formal verification has attracted a broader audience. Over the past five years, formal verification was deployed first by experts on the verification team, then by the entire verification team and lately it has been spreading to the designers themselves.
Formal verification's ability to prove with 100 percent certainty that there are no problems lurking in the shadows of a block is irresistible, once you get past the myth of it being too hard to use. The latest tools have the ability to automatically model, at a higher level of abstraction, any design components that create problems for formal technology proofs. This dramatically increases the performance and capacity for formal verification, which complements mainstream simulation to boost verification productivity. But these are just the better known aspects of how formal property verification can mitigate risk at several stages of the 45-nm design flow.
For instance, the burden of correctness is much higher for an IP block intended to be used in multiple projects. Only formal verification can achieve the level of confidence required in this case, since a bug here can impact many chips, in many products, with potentially disastrous consequences and fiscal impact.