SAN JOSE, Calif. -- Seeking to simplify and propel next-generation IC designs, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has thrown a triple-punch in the arena: It has rolled out an interoperable custom IC design kit and two unified electronic design automation (EDA) data formats.
In the first move, TSMC (Hsinchu, Taiwan) rolled out its long-awaited, interoperable process design kit (iPDK) for use in devising 65-nm custom, analog, mixed-signal and radio-frequency (RF) designs. The silicon foundry giant, Synopsys Inc. and others are also devising analog/mixed-signal PDKs for TSMC's 40- and 28-nm processes.
TSMC also unveiled two internal and interoperable unified EDA data format technologies--design rule checking (DRC) and layout-versus-schematic (LVS)--for its 40-nm process. The company's separate design rule check (iDRC) and layout-versus-schematic (iLVS) formats are said to unify the process design rule specifications and technology file generation in the IC design flow.
The iPDK, iDRC and iLVS technologies are part of TSMC's so-called Open Innovation Platform (OIP). OIP is a set of third-party EDA tools, intellectual-property (IP) blocks and other technologies to help enable and accelerate the IC design process.
In other words, TSMC is helping the IC design community at a time when chip development costs and complexity are increasing at an alarming rate. IC manufacturing and photomask costs are also soaring out of control, making it prohibitive for many to take a risk and develop new IC designs.
In fact, TSMC is pouring a huge amount of R&D dollars in its internal EDA, IP, reference flow and other efforts to help designers. The idea behind TSMC's OIP and its associated technologies is to help designers ''reduce the time to market,'' said Tom Quan, deputy director of design services marketing at TSMC.
In April, for example, TSMC rolled out two efforts in the arena. TSMC's bigger announcement appeared to be the so-called Integrated Sign-Off Flow, which is a turnkey EDA flow for 65-nm IC designs. The flow consists of specific and pre-qualified EDA and IP tools from multiple vendors, which are selected by the foundry giant.
Customers must still buy the EDA tools from the third-party vendors. But because the flow has been qualified and tuned for TSMC's fabs, chip makers can bring a product to the market more rapidly by following the pre-defined and strict guidelines in the process.
In a separate announcement last April, TSMC and EDA partner Cadence Design Systems Inc. unveiled a mixed-signal/RF reference design kit, dubbed the MS/RF RDK. Geared for 65-nm designs, the kit aims to accelerate analog, mixed-signal and RF designs in the marketplace.
TSMC has a separate effort in the analog/mixed-signal area. Last year, it joined the Interoperable PDK Libraries industry alliance. The IPL group, which includes Magma, Mentor, Synopsys and other tool and IP vendors, is pushing for a standard foundry process design kit (PDK) based on a 65-nm technology.
Today's analog-oriented PDKs are proprietary and incompatible. And in the past, TSMC was forced to support separate and proprietary custom-oriented PDKs from Cadence, Mentor, Synopsys and others.
This is costly and difficult to maintain. ''This is a lot of work and resources to make this happen,'' Quan said. The shift towards an interoperate PDK would boost ''time to market'' and reduce redundancies in the flow, he said.
Now, TSMC has made good on its promises from last year, in which the foundry vendor and IPL talked about delivering a PDK for 65-nm designs. The new iPDK supports a full custom design flow from schematic entry to final layout verification. It includes layout creation, pre-layout simulation, layout verification (DRC, LVS, ERC) and post-layout simulation.
The result is faster adoption of tools and flow that accelerate time-to-design-start for custom analog, mixed signal and RF designs. The IPL-backed iPDK will help analog/mixed-signal designers, as they move towards parts with ''higher levels of integration,'' said Ed Lechner, director of product marketing at Synopsys. ''This is the first step in improving analog design.''
As expected, the initial IPL-backed iPDK is said to support analog layout tools from all vendors over a common database, dubbed OpenAccess. It is said to interoperate with Cadence's proprietary analog environment. But some view the IPL-backed flow as a competitive threat to Cadence's analog EDA tool suite, dubbed Virtuoso.
The IPL-backed iPKD includes the following elements: OpenAccess--database and data model; Python and Tcl--open standard languages; unified symbol views; Ciranova's Pycells for parameterized layout cells; Tcl callbacks; standard component description format (CDF); and Cadence Skill callbacks to provide compatibility to Cadence IC6.1 environment.
The iPDK initiative is supported by all major EDA vendors, including Cadence, Magma, Mentor, Springsoft, Synopsys, and others. The first iPDK in 65-nm was developed in collaboration with TSMC development partners, Synopsys and Ciranova, and QA/validation partners, Magma and Springsoft.
The TSMC 65-nm iPDK will be available July 2009 in limited release and at no charge to selected customers. General release to other customers is targeted for Q4 2009. Customers may access the 65-nm iPDK at the TSMC Online customer design portal.
The IPL is not stopping at 65-nm. Synopsys and TSMC have entered into a multi-year agreement to jointly develop, validate, support and distribute interoperable iPDKs that are optimized for TSMC's 65-, 40-nm and 28-nm nodes. No timetable was given for the PDKs at the 40- and 28-nm nodes. Additionally, TSMC has adopted Synopsys' Galaxy Custom Designer implementation solution as its iPDK development and validation platform.