SAN FRANCISCOAs has been the case for the past several years, low-power design is a sure bet to emerge as one of the central themes of the 46th Design Automation Conference (DAC), set to open here next week.
Power, arguably today's No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks (for a list of some, see the DAC website). An unknown number of products will be introduced next week that focus in part or whole on helping designers create more power efficient designs.
Executives at EDA vendors and other firms agree that the focus on low-power is warranted. At advanced nodes, designers are grappling with huge challenges associated with leakage power, not to mention continuing to deal with competing power formats.
"Low power is one of the biggest challenges that designers face today," said Cary Chin, director of technical marketing for low power solutions at Synopsys Inc.
Leakage power concerns at the 90-nm node and below, combined with the demand for more functionality on portable devices, continue to push demand for techniques that lower both static and dynamic power consumption, Chin said. Below 65-nm, techniques such as power shutdown, multi-voltage design and even dynamic frequency and voltage control are becoming mainstream, according to Chin.
Designers working on ICs for wireless and handheld markets started relying heavily on techniques such as clock-gating, multi-voltage threshold swapping and multi-voltage domains at the 65-nm node, said Dan Blong, a marketing executive from Magma Design Automation Inc.'s Design Implementation business unit.
"At 40-nm and below, where leakage power is a dominant factor, designers across most market segments are focused on addressing power through better voltage domain management at the block level and careful management of clock trees through the chip," Blong said.