SAN FRANCISCONvidia Corp.'s chief scientist told the EDA community Wednesday (July 29) that chip designers need new tools to usher in a new era, moving to "throughput computing" from an era of "denial architecture" that has seen the semiconductor industry squeeze more performance out of single-thread processors thanks to software.
Delivering a keynote address here at the Design Automation Conference Wednesday (July 29), William J. Dally, chief scientist and senior vice president of research at Nvidia and an engineering professor at Stanford University, said computing is entering a world where performance increases are derived from parallelism and efficiency is determined by locality.
Chip designers will need tool and techniques to optimize power, interconnect and locality, Dally said.
|William J. Dally|
Chief scientist, Nvidia Corp.
"We are really looking to EDA to give us power tools," Dally said.
Tools are needed to enable power exploration and analysis at the architectural levels, Dally said. "I want high-level tools that allow you to gain insights into power architectures very early in design," he said.
To succeed, the industry needs CAD tools that capture high-level design and intent, as well as new architectures and compilation to expose locality, Dally said.
Interconnect is a dominant factor in power consumption, according to Dally. The emergence of optical interconnect technology may play a role, "but don't hold your breath," Dally said, citing technical issues.
Performance scaling of single-thread processors stopped in 2002, Dally said, following a period when the industry derived a performance increase of 52 percent per year for more than 20 years. But throughput-optimized processors like graphics processing units (GPUs) are still improving by greater than 70 percent per year, he said.
"Now that we are no longer scaling single-thread processors, you have no alternative," Dally said.
Throughput processors have hundreds of cores today and will have thousands of cores by 2015, Dally said. By then, Nvidia will have GPUs implemented on 11 nm process technology that feature roughly 5,000 cores and 20 teraflops of performance, Dally predicted.
The requirements of EDA tools exceed the performance increases enabled by continued compliance with Moore's Law, Dally said, and won't be sustained by improvements in single-thread processors.