MANHASSET, NY Massachusetts Institute of Technology researchers have created a chip that combines silicon transistors on the same wafer with ones made from gallium nitride, a semiconductor material that has a much better performance than silicon.
The vast majority of the transistors are made out of silicon, while GaN provides the better performance for the rest of the transistors.
Researchers have been trying to combine semiconductor materials that have different and potentially complementary characteristics into a single microchip.
Tomas Palacios, assistant professor in the Department of Electrical Engineering and Computer Science and his reasearch team have been able to combine the two materials on a single wafer. This open up the possibility of mass-producing "hybrid" chips.
Instead of trying to grow gallium nitride on top of a silicon chip as attempted by others, Palacios's team made the new hybrid chip by embedding a gallium nitride layer into the same type of silicon substrate.
The chips can be manufactured using the standard fab technology currently used for commercial silicon chips.
The faster chip is also highly efficient most of the transistors operate at slower speeds consuming less energy.
Thomas Kazior, technical director of Advanced Microelectronics Technology at Raytheon Integrated Defense Systems, said "this provides a path to RF 'systems on a chip."
The technology can also be used for combining lasers and electronic components on a single chip, and accommodate energy-harvesting devices that can harness the pressure and vibrations from the environment to produce enough power to run the silicon components.
Palacios said that cell phones, which generally use at least four or five separate chips made from different semiconductor materials, "could potentially integrate all functions on a single chip."
At present, the new technique has been used to make chips that are about one square inch in size.
Research is ongoing to overcome scaling up the process to produce these larger chips, without sacrificing quality. Conventional chip manufacturing processes typically use larger wafers, 8 or 12 inches in diameter.
"We are already discussing with several companies how to commercialize this technology and fabricate more complex circuits," said Palacios, adding that it could take a couple of years to get to the point where it could be commercialized.
The research was funded by the DARPA Young Faculty Award, the MARCO Interconnect Focus Center and the MIT Deshpande Center. Device fabrication was carried out at the Microsystems Technology Laboratories and the Nano-Structures Laboratory at MIT.
The results were initially presented in June at the Device Research Conference in Pennsylvania, and are being published in the October issue of the IEEE journal Electron Device Letters.