BOSTON It's not news that memory technology is a major driver for IC process and end-user products, and today's casual use of gigabyte-class capacities in mundane consumer products is solid evidence of that reality.
At the Embedded Systems Conference-Boston, Glen Hawk, vice president and general manager of the Embedded Business Group at Numonyx, explained how changes in memory technologies affect designers and products, and how the coming reality of phase-change memory will again change the design tradeoffs at both the prototyping stage as well as for final products.
While Numonyx is just an 18-month-old company, formed from spin-outs of Intel and STMicroelectronics supplemented by funding from Francisco Partners, it has nevertheless emerged as the third-largest vendor of flash devices, Hawk noted.
Regardless of feature size, Hawk noted there is a cost floor for the two flash memory approaches due to their need for internal overhead for functions like charge pumps, error correction circuitry and I/O. In the case of NAND, he cited $2 as the floor, while it's around 50 cents for NOR. The production window must also be considered, where volume and cost overlap the peak of the production and cost-efficiency curve among memory vendors.
Nevertheless, Hawk stressed that the next game-changer for designers is phase change memory (PCM). Unlike previous technologies, which use captured and controlled electrons in some way (with fewer available with each process shrink, to the point of on-the-edge unreliability at the bit level). PCM stores bits by transitioning between amorphous and crystalline states of relatively common chalcogenide glass, which is a physical property.
He rated PCM as positive in terms of bit alterability, scalability, read speed, software-related complexity and endurance. But there are challenges, including concerns about the cost-per-bit and write speed.
Hawk suggested that designers start, as they did with Eprom by using PCM for prototypes, where there is an immediate savings in time to reprogram due to its bit-level alterability (in contrast to the block erasability of NOR and program page erasability of NAND).
For a 512-Mbyte memory, he noted, typical "reflash" time drops from between 3 and 4 minutes to about 30 seconds. What hard-pressed designer, up against deadline and struggling with a cranky prototype that needs serious debugging, couldn't use that gain?