LONDON The IMEC research center (Leuven, Belgium) and its 3-D integration partners have taped-out Etna, a 3-D chip that integrates a standard DRAM chip on top of a logic IC. The 3-D stack consists of a 25-micron thick logic die on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps.
Partners in IMEC's 3-D integration include Amkor, Infineon, Intel, Micron, NEC, NXP, Panasonic, Qualcomm, Samsung, STMicroelectronics, Texas Instruments and TSMC.
The 3-D demonstrator includes heaters to test the impact of hotspot on DRAM refresh times. And, the chip contains test structures for monitoring thermo-mechanical stress, electro-static discharge hazards, electrical characteristics of TSVs and micro-bumps and fault models for TSVs.
One of IMEC's 3-D integration partners will deliver the DRAM dies presumably Micron and will test the fabricated 3-D stack; two other partners, will package the 3-D stack using flip-chip onto a FBGA (fine-pitch ball-grid array) substrate.
"We are excited to achieve this milestone in collaboration with our 3D integration partners including memory suppliers and IC manufacturers.
This test-chip is a significant step for the introduction of 3D technology in DRAM-on-logic applications;" said Pol Marchal, principal scientist 3-D integration at IMEC.
IMEC has a so-called Pathfinder project with Qualcomm, AutoESL, Javelin Design Automotion on design for 3-D integration.
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Qualcomm joins IMEC's 3D group
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