SAN FRANCISCOResearchers from Intel Corp. and its flash memory joint venture, Numonyx BV, have demonstrated the ability to stack multiple layers of phase-change memory (PCM) arrays within a single die, a breakthrough that could pave the way for PCM to one day displace multiple existing memory technologies in various applications, the companies said Wednesday (Oct. 28).
On a 64-megabit test chip, researchers say they were able to demonstrate a vertically integrated memory cell dubbed phase change memory and switch (PCMS). This cell is comprised of one PCM element layered with ovonic threshold switch (OTS) in a true cross-point array, according to the companies.
A paper describing the breakthrough is scheduled to be presented at the International Electron Devices Meeting (IEDM) in December.
According to Al Fazio, an Intel Fellow who directs the firm's memory technology development efforts, the ability to layer or stack arrays of PCMS should provide scalability to higher memory densities while maintaining the performance characteristics of PCM. Because it has been demonstrated to be stackable, the PCMS technology could one day displace NAND flash memory, which is not stackable, as well as other current memory technologies, Fazio said.
Fazio and Greg Atwood, senior technology Fellow at Numonyx, characterized the breakthrough as an early research milestone and suggested that a product based on PCMS is still years away. In order for PCMS to get to become a successful product it will have to prove its scalability and prove it has other "product-like capabilities," Fazio said. Eventually it would also need to compete against established memory technologies that have established economies of scale, he added.
Phase-change memory has long been viewed as an attractive long-term technology for non-volatile memory. But despite years of research, PCM in product form is barely out of the gate and has yet to show any signs of significant adoption. Many in the industry remain skeptical of PCM, voicing concerns over the cost-per bit, scalability of the technology and ability to meet write-speed requirements.