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Researchers detail new power management technique

11/2/2009 10:00 PM EST
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DashawnX
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re: Researchers detail new power management technique
DashawnX   11/7/2009 9:45:48 AM
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Multi Core Processor Designs are currently the state of the art in processor design, with some having as many as 100 cores in them. These offer record-breaking throughput with power consumption reaching 55 Watts. On the other side are mobile processors for laptops and netbooks and embedded processors, increasingly being found in hand held devices like the iPhone, where power consumption is the main bottleneck in achieving higher processor speeds. What if we marry the two concepts together, to make a dual core embedded processor, with one low power core and another high power. The low power core does all of the usual work once the cache / RAM is fully loaded and the high power core idles at this time - giving the power consumption of a single core processor for most of the running time. In case an instruction asks for information not on the Cache / RAM, the high power core can be kicked into action to do the needful. Haven't read of such a design till now, most of the power management schemes involve dynamic voltage scaling, which has its own reliability concerns. What do you think would be the drawbacks of such a design? Do you think this kind of processor design can be successful even without using any short term loan?

Nirav Desai
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re: Researchers detail new power management technique
Nirav Desai   11/4/2009 11:54:49 AM
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Multi Core Processor Designs are currently the state of the art in processor design, with some having as many as 100 cores in them . These offer record breaking throughput with power consumption reaching 55 Watts. On the other side are mobile processors for laptops and netbooks and embedded processors, increasingly being found in hand held devices like the iPhone, where power consumption is the main bottleneck in achieving higher processor speeds. What if we marry the two concepts together, to make a dual core embedded processor, with one low power core and another high power. The low power core does all of the usual work once the cache / RAM is fully loaded and the high power core idles at this time - giving the power consumption of a single core processor for most of the running time. In case an instruction asks for information not on the Cache / RAM, the high power core can be kicked into action to do the needful.. Haven't read of such a design till now..most of the power management schemes involve dynamic voltage scaling, which has its own reliability concerns. What do you think would be the drawbacks of such a design ? Do you think this kind of procesor design can be successful ?

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