SAN JOSE, Calif. MoSys Inc. said Tuesday (Feb. 2) it will make memory chips using a novel high-speed interface for a broad range of networking and storage markets. The Bandwidth Engine is the first of a planned family of standard parts for the company that is expanding beyond its roots as a supplier of silicon cores.
The new chips will debut late this year using 65nm technology to offer densities of 576 Mbits. Using 16 ports of 10.3 Gbit/second serdes interfaces, they will deliver up to two billion memory accesses a second.
The chips will outrun today's 533 MHz reduced-latency DRAMs while using less than half the die area, power and cost, the company claimed. Indeed, one Bandwidth Engine chip aims to replace two or more RLDRAMs and quad-data-rate SRAMs used to handle statistics and decision tables in existing system designs.
By early 2013, the company hopes to use 28nm technology to deliver 2,304 Mbit chips delivering four billion accesses per second. The memory chips could feed ASICs and network processors in a broad range of routers, switches and storage networking systems rapidly shifting to 40 and 100 Gbit Ethernet.
"This could be a billion-dollar opportunity," said Dave DeMaria vice president of operations for MoSys. "It will take some time to ramp, but it's a long term business because these systems typically have ten-year lifecycles," he said.
That's a big target for a company on a current run rate to rack up a little more than $20 million in annual sales. MoSys has been posting losses for several quarters, in part due to its expenses developing the new product line.
"We wanted to go public with our plans so our shareholders can see we've been investing in this and changing our business model," DeMaria said.
MoSys will have to convince OEMs to rely on it for critical components. That will require creating a full eco-system of supporting vendors including ASIC, FPGA and tool vendors, something MoSys said is in the works.
The company plans to create an ad hoc consortium supporting its so-called Gigachip Interface. The technology is based on the Common Electrical Interface defined by the Optical Internetworking Forum controlled by what MoSys described as a "very lightweight protocol" it has developed
"We looked at serial error detection and recovery protocols from PCI Express to Interlaken and decided for short reach point-to-point chip-to-memory, they all were carrying extra overhead we didn't need," said Michael Miller, vice president of technology innovation and systems applications at MoSys.
"We only need a handful of [vendor] companies to support [the protocol], and we believe we'll get their support," said DeMaria. "We can't say any OEMs are adopting it yet, but the initial response has been very positive," he said.
The transition to being a fabless semiconductor company started when former IDT head Len Perham took the helm at MoSys in early 2008. Perham sought ways to leverage the company's memory technology to address problems in networking he had become familiar with as chairman of chip designer NetLogic Microsystems.
In December 2008, MoSys exited the analog IP business and cut 90 employees. In June 2009, it acquired startup Prism Circuits for its 10 Gbit serdes technology needed to fuel its emerging memory-chip plan.