LONDON Professor Jean-Pierre Colinge of Tyndall National Institute (Cork, Ireland), co-author of the paper Nanowire transistors without junctions that was published by Nature Nanotechnology recently, has said that junctionless transistors could be implemented commercially at around the 20-nm manufacturing node.
The junctionless transistor is based on use of control gate around a silicon nanowire. The gate can be used to modulate the resistance of the nanowire and to "squeeze" the electron channel to nothing, thus turning off the device. Doping is used to produce p- and n-type FETs but there are no steep dopant gradients nor junctions, which promises simplified manufacturing.
Such a major change in the structure of the fundamental electronic device could be expected to require a great deal of independent research. An introduction at or around 20-nm would require companies to switch more or less immediately. However, a switch to the junctionless transistor could fit in with previously forecast moves by the industry away from planar transistors and towards FinFETs and multi- and wrap-around gate structures.
Speaking to EE Times by telephone Professor Colinge said: "It's not shown in the Nature paper but we have made a silicon nanowire measuring about 10 nanometers by 10 nanometers. Now there is a rule of thumb that the gate length should be about twice the nanowire dimensions to avoid short channel effects. I think junctionless transistors could intersect with ITRS [International Technology Roadmap for Semiconductors] at 20-nm."
Professor Colinge continued: "The junctionless transistor could compete now but it will take time for semiconductor companies to get used to the idea. People are scared of the high doping levels."