SAN JOSE, Calif. -- After several false starts, the industry appears to have finally paved a roadmap for interoperable process design kits (PDKs).
Short term, the PDK path looks clear. Long term, it looks less clear. The progress depends upon the companies involved, some of which agree to disagree on the technology.
For now, there is a path towards an ''open'' PDK, which is said to enable and speed up new analog and mixed-signal designs in the foundries.
On Wednesday (Feb. 24), the Interoperable PDK Libraries (IPL) Alliance will release its long-awaited ''open standard'' for interoperable process design kits (iPDKs). The standard, dubbed IPL1.0, is supposed to reduce cycle times and costs.. As part of the standard, IPL is rolling out an IPL1.0 reference kit, which consists of an iPDK developer's guide, a sample 90-nm reference iPDK, a reference design and a user guide.
Based on the OpenAccess database, the technology from the IPL Alliance will continue to evolve over the various process nodes. Then, the Silicon Integration Initiative (Si2) recently said that it is working with the IPL Alliance to extend ''open PDKs'' starting at the 22-nm node.
Today, IPL1.0 is the starting point for open PDKs. ''This is open for the whole industry,'' said Jingwen Yuan, strategic alliance manager at Synopsys Inc., one of the driving forces behind IPL.
In the past, each foundry had to create specialized PDKs for each and every EDA vendor. This is expensive to maintain for the foundries. In contrast, using IPL1.0, PDK development teams need to only develop a single PDK for each process node, thereby reducing development costs and cycle times, said Kevin Kranen, director of strategic alliances for Synopsys and Michael Ma, vice president of business development at Ciranova.
Open PDKs are easier said than done. The industry has been talking about a standard PDK format for years, but many of the previous efforts have fallen short and failed.
IPL believes it has the right formula. The IPL Alliance was started in 2007, with five founding members: AWR, Ciranova, SpringSoft, Silicon Navigator and Synopsys. Mentor Graphics and Pulsic joined as supporting members. The newest members are the following entities: TSMC, Helic, JEDAT, Magma, Micro Magic and Virage Logic. Recently, LFoundry, TowerJazz and others joined the group.
A PDK, as defined by the IPL, is a set of technologies to enable a complete analog and mixed-signal design flow. This consists of foundry-verified data files, such as schematic symbols, component descriptions, parameterized cells (p-cells) and callbacks. The p-cell library is based upon Ciranova's PyCell Studio, built around a programming language called Python.
Not all are on board with IPL, however. One EDA vendor, Cadence Systems Design Inc., refuses to join IPL and views the IPL-backed flow as a competitive threat to its analog EDA tool suite, dubbed Virtuoso.
Cadence dominates the custom EDA landscape. Cadence's p-cell libraries are written in a rival and proprietary language called Skill, which is said to lock customers into Virtuoso.
IPL is attempting to break Cadence's monopoly in custom design, but the group has also tried to reach out and work with the EDA vendor. ''Although Cadence has not yet chosen to join the IPL group, members have tested the proof-of-concept library with Cadence Virtuoso 6.1,'' according to the IPL Alliance.
Still, IPL gained traction last year, when Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) made good on its promise to deliver a PDK for 65-nm designs. The new so-called iPDK from TSMC supports a full custom design flow from schematic entry to final layout verification.
TSMC is still working on the first 65-nm designs based on the PDK and is also devising the technology for the 45- and 28-nm nodes, said Tom Quan, deputy director of design methodology and service marketing at TSMC. ''From a foundry perspective, the PDK will allow us to save a lot of cost,'' Quan told EE Times.
Following the original TSMC announcement, the IPL group has been working on releasing a standard PDK. Ciranova, SpringSoft, Synopsys and TSMC were major contributors to the release and validation of IPL1.0. Synopsys was the lead developer of the sample 90-nm reference iPDK and reference design.
The IPL1.0 reference kit was validated in multiple custom design flows and tools by IPL Alliance members. The validation process covered a comprehensive set of tests including schematic capture, circuit simulation, layout, physical verification and extraction.
Using IPL1.0, foundries and integrated device manufacturers (IDMs) can use this standard to build a single PDK that work with multiple OpenAccess-based custom design tools. EDA vendors can use this standard to validate that their tools work with the iPDKs delivered by the foundries and IDMs.
IPL1.0 reference kit is available for immediate, free download under the open source licensing agreement at IPL Alliance web site.