LONDON eASIC Corp. (Santa Clara, Calif.) has said it can supply the Leon4 processor from Aeroflex Gaisler AB (Goteborg, Sweden) as part of its eZ-IP Alliance Core Library.
The Leon4 is a 32-bit processor core based on the Sparc V8 architecture. Leon4 is software compatible with previous Leon processors and comes in single- or dual-core versions. It implements single-cycle load/store instructions, as well as static branch prediction. The register file and internal load/store data paths have been extended to 64-bits, while the data cache and bus interface can be either 64- or 128-bit wide. An optional level-2 cache has also been added to the architecture, further improving performance on data intensive and multi-core applications. The Leon4 processor delivers up to 1.7 dhrystone MIPS per megahertz or 0.35-SPECinterger2000 per megahertz, eASIC said.
Leon started out as an open-source non-royalty design for use in space by the European Space Agency, however it has sinced been designed into many industrial applications.
"We are pleased with the performance of this next-generation processor on eASIC silicon," said Jiri Gaisler, CTO and founder of Aeroflex Gaisler, in a statement issued by eASIC. "The low cost-point and low up-front development cost of eASIC devices coupled with our Leon4 embedded processing sub-systems now enable an excellent price/performance entry point for custom embedded chip designs."
"The Leon4 processor core provides our customers with a perfect alternative to traditional soft processor cores from FPGA vendors and prevents customers from being locked into proprietary FPGA vendor IP cores," said Jasbinder Bhoot, vice president of marketing at eASIC, in the same statement. "With Gaisler, customers are provided complete solutions that include CPU cores, peripherals, software tool chain, development boards and technical support."
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