SAN JOSE, Calif. Researchers have taken several small steps on a long and complex journey toward creating new parallel programming models to harness tomorrow's many-core processors. The work entails crafting an entirely new set of architectures ranging from parallel applications and data structures to the processors that will run them.
That was the picture that emerged from more than a dozen presentations from the Universal Parallel Computing Research Center (UPCRC). The group, funded by a five-year $10 million grant from Intel and Microsoft, concluded a two-day summit Friday (March 19) at the University of Illinois.
The summit was essentially an interim update on a work plan the two-year-old center sketched out in a white paper released in November 2008. The update showed researchers have largely kept to their master plan, are tightly engaged with their Wintel sponsors and still have a long way to go.
The center consists of 18 principal investigators, two research programmers and 33 graduate assistants. It parallels industry-funded work going on in separate centers at Berkeley and Stanford. All three efforts aim to beat a path to the kinds of parallel applications, tools and silicon architectures that programmers will need to harness tomorrow's chips.
The summit gave updates on three separate processor projects, two of them still in an early stage of defining their architectures. All three are attempts to test out new concepts for a coming world of general-purpose chips built up from hundreds of cores.
The newest and perhaps most ambitious of the trio, called DeNovo, is an effort to define a new and more disciplined way of using shared memory. It is working in tandem with a separate project to define a deterministic, parallel language initially based on a parallel version of Java and ultimately migrating to a parallel version of C++.
Researchers believe today's techniques using threads and locks to program multicore processors will not scale to chips with dozens of cores. The new languages represent efforts to craft approaches that many believe will require new kinds of memory structures in software and silicon.
"Several of us believe today's shared memory model is fundamentally broken," said University of Illinois researcher Sarita Adve, working on DeNovo. "We still want a global address space, but we need a more disciplined programming model with more explicit structures and effects," she said.
Adve and others are defining test applications such a system should be able to run to help define the kinds of memory and coherency structures the DeNovo processors should adopt. Some of the hardware concepts have been tested in simulation and others have yet to be implemented, she said.
Slides for the talks are available online.