PARIS The SOI Industry Consortium has launched the 'Ready for SOI Technology' program to stimulate adoption of energy-efficient silicon-on-insulator (SOI) technology. A cornerstone of the program is education.
Initiated by IBM, ARM and Cadence, the 'Ready for SOI Technology' program aims to provide chip and system designers access to SOI design intellectual property (IP) and make this IP available through a SOI portal hosted on the ChipEstimate.com website.
And, to enable the formation of a complete ecosystem that enables designers to take full advantage of the benefits of SOI technology, IBM, ARM and Cadence decided to deliver educational tools such as trainings and seminars.
A survey conducted by the Global Semiconductor Alliance (GSA) and the SOI Consortium in 2008 highlighted the need for more SOI education and awareness. A question indeed asked what the biggest reason was for not evaluation or using SOI today, and the top reason cited was the perceived additional cost of SOI, followed by lack of design knowledge and then risk and IP availability.
This survey proved that education is key to reducing barriers to adoption, confirmed the need for a group dedicated to SOI to provide the knowledge and expertise needed to inform the industry and debunk present misconceptions.
"Making sure that we educate people is precisely what we are trying to do," stated Horacio Mendez, executive director of the SOI Industry Consortium. "Education is a broad perspective. We are trying to educate designers on how to design with SOI but also on how they can access the IP and the advantages of SOI."
Remy Pottier, marketing and business development at ARM, further stated: "Moving to SOI in terms of design is quite simple with regard to what we have proven with the ARM 1176 implementation we did. The team had no clue about what was SOI. Actually, we did the tape-out in the same time frame as in bulk so it is nothing specific to learn or complex to understand."
He added: "From a SoC designer perspective, it is very simple. For an IP provider, there are some effects that need to be taken into account when you design physical IP like standard cell memory. These effects are very well-known, but we think that it makes sense to have a training to get some IP providers to understand the specificities of SOI so that they can really take them into account when they design their own IP. So, the training is for designers, of course, but also for IP providers to understand what is possible with SOI."
In a view to help IP and chip designers transition to SOI, the Ready for SOI Technology program is promoting SOI Jump Start Training for IP and Chip Designers on April 28, 2010, with the option of attending a live event in Silicon Valley, hosted by Cadence, or online in a simulcast or recorded webinar.
"We are inviting all IP suppliers on ChipEstimate.com and anywhere else to join the training so that they can get familiar with the technology," said Susan Runowisc-Smith, Cadence's Group Director, Ecosystem Enablement Marketing.
Further trainings are planned, said Mendez. "We are making available online a seven-part design training clinic. We expect to launch it in the first week of April, perhaps a little earlier but it will be available online on the consortium website."