MANHASSET, NY At the TSMC Technology Symposium in Silicon Valley this week Virage Logic announced a full suite of 28nm memory compilers and logic libraries based on TSMC's high-K metal gate process.
In late 2009, Virage Logic announced its first 28nm test chip tapeouts.
"With Virage Logic memory and logic already in mass production on 40nm at TSMC, customers can rely on our proven track-record for their 28nm designs," said Brani Buric, Virage Logic executive vice president of marketing and sales," in a statement.
Virage Logic's SiWare Memory supports all major system-on-chip (SoC) power management techniques including Dynamic Voltage Frequency Scaling (DVFS), optional/selectable transistor threshold implants, and multiple standby power management modes that can save 50-90 percent standby power, according to the company.
Process nodes such as 40nm and 28nm require advanced characterization methods to properly simulate the effects of process variation. To that end, Virage Logic has developed AutoChar, a compiler and instance based characterization system, to reduce time to develop and deploy memory compilers. This software characterization suite is allows designers to explore an array of process, voltage and temperature (PVT) dimensions.
Virage Logic's logic libraries maximize yield by adhering to restrictive design rules and multiple contacts for the highest manufacturability and robust electro-migration standards for reliability. Local variations are minimized with uniform layouts, use of non-minimum sized devices, and are accurately characterized in foundry-specified extraction environments that reflect DFM effects such as Well Proximity Effect (WPE) and diffusion spacing with neighboring circuits.
Front-end SiWare Memory compilers are available today starting at $130,000 for a single compiler project, which also includes logic libraries, for early adopters of TSMC's 28HP process. Full memory compilers will be available to the general public in June 2010 and logic libraries will be available in Q3 2010.
The company also expanded its portfolio of multi-time programmable (MTP) non-volatile memory (NVM) with the qualification of AEON MTP Parallel NVM at TSMC.
AEON MTP Parallel NVM now available in 130-nanometer (nm) G process is targeted at analog mixed-signal applications now migrating from 180nm down to 130nm.
AEON MTP Parallel NVM provides a reprogrammable non-volatile memory solution to trim precision ADC (analog to digital converters) and DAC (digital to analog converters), to store encryption/decryption keys, and to configure MEMS devices.
AEON MTP Parallel NVM is ideal for use in portable devices, such as multi-function cell phones that require NVM for precision analog trim values to optimize the performance of the audio, display, or sensor IC in an on-board accelerometer and gyroscope.
The NVM also serves to provide encryption key storage for digital rights management (DRM), configuration settings for Bluetooth or WiFi connections, and custom personalization settings in baseband processors.
Market research firm iSupply estimates that 1.2 billion mobile devices shipped in 2009 and projects the shipment to reach 1.5 billion units in 2012.
"Virage Logic customers can easily migrate their designs from one TSMC process node to another without having to change their NVM solution," said Yankin Tanurhan, vice president and general manager of Virage Logic's processor and NVM solutions business units.