SAN JOSE, Calif. -- Seeking to take the technology lead in the silicon foundry business, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is putting a new spin on its strategy: After the 28-nm node, it plans to skip the 22-nm ''full node'' and will move directly to the 20-nm ''half node.''
At its technology conference here, the world's largest silicon foundry also provided details about its 20-nm CMOS process, which will be the company's main technology platform after the 28-nm node. TSMC will also not offer an 18-nm process.
TSMC's 20-nm process is a 10-level metal technology based on a planar technology. It will feature a high-k/metal gate scheme, strained silicon and newfangled ''low-resistance'' copper ultra-low-k interconnects--or what it calls ''low-r.'' For the 20-nm node, it will only offer a high-k/metal-gate scheme for the gate stack--and not a silicon dioxide option.
TSMC (Hsinchu) will continue to use 193-nm immersion lithography at 20-nm, but it will also deploy a double-patterning and source-mask optimization schemes. Unlike its previous processes in recent times--which focused on low power first--TSMC's initial 20-nm process will be a high-performance technology. Following that process, it will roll out a low-power technology.
With the announcement, TSMC is seeking to gain an edge over its leading-edge rivals, such a GlobalFoundries, Samsung and UMC. Both Samsung and UMC have said little or nothing about their respective 2x-nm nodes.
By going to 20-nm, TSMC is leapfrogging one rival--at least on paper. Recently, GlobalFoundries Inc. said it is starting work on its 22-nm CMOS process, which is due out in the second half of 2012. TSMC is also looking at the second half of 2012.
In comparison, Intel Corp. is expected to be at the 22-nm node by the fourth quarter of 2011. As for which vendor is leading in the foundry race at 2x-nm, it's unclear until a company ''beats the drum and announces they are in production,'' said Dean Freeman, an analyst with Gartner Inc.
Meanwhile, TSMC is taking a different approach with its process nodes. In the past, TSMC marched down a predictable process path, as defined basically by the ITRS roadmap. Then, it would generally offer a ''half-node'' process as a means to migrate customers to the next node.
As of late, TSMC generally pushed its customers to the half-node process, possibly as a means to differentiate itself. For example, TSMC rolled out a 32-nm process, but it will move customers over to the 28-nm technology.
At one time, it was widely believed that TSMC would offer a 22-nm node. ''22-nm was an option for customers, but we decided to skip it,'' said Shang-yi Chiang, TSMC's senior vice president of research and development. In an interview, Chiang said that the move to 20-nm creates a better gate density and chip performance to cost ratio than a 22-nm process technology.
At the 2x-nm foundry node, cost and complexity will continue to escalate for customers. In recent times, TSMC has provided process flows, design kits and intellectual property (IP) to help reduce foundry costs. ''Customers must engage with us at a much earlier stage'' at 20-nm to reduce costs and complexity, Chiang told EE Times.
An IBM researcher recently warned of "design rule explosion" beyond the 22-nm node during a paper presentation earlier this month at the International Symposium on Physical Design (ISPD). Kevin Nowka, senior manager of VLSI Systems at the IBM Austin Research Lab, described the physical design challenges beyond the 22-nm node, emphasizing that sub-wavelength lithography has made silicon image fidelity a serious challenge.