TSMC's 20-nm process features 10-level metal layers, although customers may typically use 6-to-8 layers, he said. The company continues to push bulk CMOS silicon at 20-nm, as it will not migrate to silicon-on-insulator (SOI) or other transistor structures such as FinFETs.
Chiang believes that 20-nm could be the last node that TSMC uses a planar structure. Following that node, possibly 14-nm, TSMC may be forced to go to a FinFET or a 3-D structure.
Like its 45-, 40-, 32- and 28-nm processes, TSMC will use 193-nm immersion lithography at 20-nm. At that node, it will likely use one or more forms of double patterning, source-mask optimization and other technologies. Its main lithography vendor is ASML Holding NV.
At that node, TSMC is also evaluating other lithography candidates, namely EUV and maskless. The foundry provider will initially go with 193-nm immersion at 20-nm production, but it may also deploy EUV or maskless in 2013-to-2014, depending on the viability of those technologies, he said.
ASML recently said that TSMC will take delivery of ASML's extreme ultraviolet (EUV) lithography system. At some point, TSMC will take delivery of a TwinScan NXE:3100 tool from ASML. The NXE:3100 is a ''pre-production'' EUV tool, said to have an NA of 0.25.
In addition, TSMC and Mapper Lithography BV recently claimed that Mapper's multi-beam e-beam tool located on TSMC's Fab 12 GigaFab is printing features so far unachievable with current immersion lithography. In 2008, TSMC and Mapper concluded an agreement according to which Mapper would ship its first 300-mm multiple-electron-beam maskless lithography platform for process development and device prototyping to TSMC.
At 28-nm, the company is supposed to roll out its first high-k/metal-gate scheme for the gate stack. At that node, it will also offer a silicon dioxide option. So far, TSMC's high-k technology is progressing, he said.
Meanwhile, at 20-nm, TSMC will deploy its fifth-generation strain engineering technology and its second-generation high-k/metal-gate scheme. For 20-nm, TSMC will only offer a high-k/metal-gate technology. It will not offer a silicon dioxide scheme for the gate stack.
Originally, TSMC was planning to go with a gate-first high-k technology. Now, it will go with gate-last. There are two basic approaches to the next-generation gate stack in logic designs. IBM's ''fab club'' is using a gate-first approach, while Intel is deploying a rival replacement-gate or gate-last technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.
''The real key difference in the gate-last approach (is that) we use two different gate metals, one metal for the P channel and one metal for N channel. For the gate-first approach, we use the same metal for N and P channel. In gate-last, we can freely adjust voltage for both N channel and P channel. Gate-first has difficulty doing that. So that's a major difference,'' Chiang said in a recent presentation.
For years, TSMC has deployed low-k dielectrics, based on Applied Materials Inc.'s Black Diamond technology. At 28-nm, TSMC is using a carbon-doped oxide process with a ''k'' effective number of 2.6.
At 20-nm, TSMC will use an in-house low-k material. the ''k'' effective number will move to 2.3. ''Pushing low-k is very difficult,'' due to the porous materials and packaging issues, he said.
So instead of pushing the constant, TSMC is taking another approach: It is moving to ''low-r'' instead of low-k. ''We will lower the resistance rather than pushing the capacitance,'' he said.
Going is towards lower resistance in the interconnect is ''not surprising,'' said Gartner's Freeman. ''You will also see new barrier seed materials at 20,'' he said.