PORTLAND, Ore. Columbia University researchers are working on a new testing regime for evaluating the failure parameters of low-k dielectric insulators in chips.
The testing is being developed for research consortium Semiconductor Research Corp.
"Technologists typically tend to keep building new devices with subtle tweaks based on intuition until they find the solution," said Robert B. Laibowitz, senior research scientist at Columbia University. "We are looking directly at how the fundamental physical properties of the insulator material itself are being affected."
"By doing so, we believe we can find and fix many of the insulator reliability issues and help extend the lifetime of the chips," said Laibowitz.
"Low-k dielectric materials usually have a lot of porosity, and sometimes include organic materials like carbon, both of which can generate defects which trap electrons," said Scott List, director of Interconnect and Packaging Sciences at SRC.
Traps in a low-k dielectric material generate a leakage through the insulator that generates excess heat causing short circuits.
SRC commissioned Columbia University to create a testing regime that can evaluate low-k dielectric materials with short, easy to perform tests.
Usually engineers perform a time dependent dilelectric breakdown (TDDB) test where they look at leakage as a function of time, mapping out how long it takes the dielectric to fail but not revealing the underlying mechanism.
Columbia researchers found a method that works better by actually measuring the average number of density traps inside low-k dielectrics, enabling the breakdown mechanism to be more easily identified.
Columbia researchers have been testing low-k dielectrics samples from IBM, Intel, Freescale and other semiconductor makers in its testing regime.
The 3-year SRC contract runs through Jan. 2011 at which time Columbia University will deliver to SRC members the new testing regime.