AUSTIN, Texas The 90-nanometer horses are off and running as chip makers race to be first to market with products built using next-generation process technology.
Texas Instruments Inc. said Wednesday (Jan. 22) that it has delivered engineering samples of a wireless digital baseband IC to a leading customer, believed to be cell phone maker Nokia, crafted in TI's 90-nm process. The process delivers 4.8 million transistors, or 800,000 6-T SRAM bits, per square millimeter, and supports a 37-nm gate length.
IBM Microelectronics announced last month that it had taped out a Xilinx FPGA at 90-nm design rules, and Toshiba Corp. recently said it would commence early 90-nm system-on-chip production toward the middle of this year. Intel Corp. expects to begin making its Prescott microprocessor late this year on its 90-nm process, which includes a layer of strained silicon to enhance mobility.
Advanced Micro Devices Inc., Motorola's Semiconductor Products Sector, foundries Taiwan Semiconductor Manufacturing Co. and United Microelectronics Corp., and others are rushing to bring 90-nm products to the market by year's end.
Ben McKee, the 90-nm team leader at Texas Instruments (Dallas), said the baseband IC will go through a period of testing and system debug before moving to volume production at TI's 200-mm Kilby fabrication facility in Dallas in the fourth quarter. The design will be transferred to the company's DMOS-6 300-mm fab in the first quarter of 2004.
TI strove to keep the chip simple, eschewing silicon-on-insulator or strained-silicon process enhancements.
"The main challenge in developing the 90-nm technology was to get the analog transistors, the design infrastructure, all of the 'care abouts' done in a way that avoids complexity," McKee said. "You can't afford to add too much process complexity because it gets very costly. Particularly for RF CMOS, you have to work very hard on the design infrastructure and simulation aspects so you have a good design path and don't get surprised down the road."
The analog and RF devices will be needed for forthcoming mixed-signal products. Peter Rickert, director of process technology development for TI, said that by June the company expects to be prototyping multiple devices at 90-nm design rules.
Moving to 300 mm
Also this summer, TI engineers will start to bring the process up at the DMOS-6 300-mm wafer fab here for qualification in the first quarter of 2004. Rickert said that in the current quarter TI will produce "a significant number of wafers, because we require at least 10,000 devices for early failure analysis."
The shrink to a 90-nm process reduces by 50 percent the silicon area of a design built with a 130-nm process, and the 300-mm wafers deliver about 2.4 times the total area of a 200-mm wafer. The combination of the two will result in significant cost reductions, McKee said.
Rickert said that TI will have "three flavors of 90 nm." One is for "low-cost embedded low-power applications, such as the baseband we are making today. A second flavor will suit TI high-performance DSPs at, say, 750 MHz." The third flavor, he said, "is for the foundry business and enables Sun Microsystems' UltraSparc gigahertz CPUs." Added Rickert, "We are able to get to a couple of gigahertz without using strained silicon."
TI's 90-nm process makes it possible to use transistors "tuned" for different functions on a single chip, meeting a variety of performance, density and power consumption requirements. Rather than use more exotic process enhancements, Rickert said TI chose to adjust the gate length, threshold voltage, gate oxide thickness and bias conditions of the transistors.
The process supports operating voltages from 1 to 1.4 volts, though McKee said some designers may choose to work at well below 1 V to reduce power consumption.
TI is adopting the Coral low-k dielectric, an organo silicate glass material from Novellus Corp. with a k-value of 2.8, for the nine levels of interconnect supported by the process. TI gained experience with Coral by first using it for the high-performance 130-nm (0.13-micron) process that's used to make the UltraSparc processors.
McKee said that while TI has used 193-nm scanners for its 130-nm products, the use of 193-nm tools will expand at the 90-nm node. For the baseband IC, 193-nm scanners were used for 10 mask layers, including two transistor-formation layers and the first four layers of interconnect.
Phase-shift masks (PSMs) were required for the gate-formation and contact-hole layers, including one alternating PSM and several attenuated PSMs. Alternating PSMs require two complementary mask layers, and are far more expensive than attenuated PSMs.
McKee said TI introduced nickel silicide, with an improved sheet resistance, moving away from the cobalt silicide used to enhance electrode performance at earlier process nodes. The nickel silicide works much better at short gate lengths, he said.
In 2005, TI expects to introduce a ferroelectric memory module to the 90-nm process. TI claims that the process will deliver a cell size of 0.35 micron2, with only two additional mask layers.
Peter Clarke is an editor with Semiconductor Business News, an EE Times Network Web site.