Advanced Micro Devices Inc.'s chief scientist and senior vice president of technology operations, Bill Siegle, detailed his company's plans to co-develop future-generation process technology with IBM Microelectronics, in a telephone interview with EE Times editor-at-large David Lammers.
Bill Siegle: Let me give you a short overview first. This is a multi-year deal which includes 65- and 45-nanometer technologies, accomplished on 300-mm wafers. And it is with IBM, a partner whose own products, servers and other products, mirror very closely the demanding performance requirements that we have at AMD. And the joint development work will be accomplished at one place, one facility, at substantial economies. This is part of our effort to reduce costs and get our break-even point down, and build a relationship with a partner that can help us maintain an aggressive performance road map.
EE Times: How much is AMD paying IBM?
Siegle: We don't discuss specific financial terms. If we sum up all the spending over the multi-year time frame, it is a sizeable amount of money. But it is expensive no matter how you go at it. This is a way to get to 300-mm that is a hell of a lot cheaper than any other arrangement we could have contemplated. Both companies have an interest in strained silicon on SOI silicon-on-insulator, so it is more efficient than doing our own thing.
EET: What about your deal with AmberWave Systems on strained silicon?
Siegle: The work we have done with AmberWave is an initial phase on bulk not on SOI, and that has come to a natural completion phase. We are talking to them about how we might go forward, but that discussion will have to fit in with the IBM relationship. We are in a natural transition point.
EET: Is strained silicon on SOI the leading candidate for AMD and IBM at the 65-nm node?
Siegle: If look at where we are, in the first month of '03, with 65-nm production late in '05, we are still in the phase of evaluating technology options. The IBM program is in a similar state. Both of us would like to reach the conclusion that strained silicon on SOI can be implemented. It is not a definitive decision, it is one of the options that are in the hopper. The advantages of strained silicon and the advantages of SOI are somewhat independent, and if we put them together we have got a real world-beater.
We have to be careful not to reduce the strain during processing. That is one of the reasons it is just one of candidates. We are not far enough down the learning curve to make that decision.
EET: The SOI wafers are still fairly expensive?
Siegle: Yes, the SOI wafers are expensive, and strain adds another kicker. That is part of our consideration: can it be ready not only technically but in terms of cost?
EET: What do you plan for the low-k road map? IBM and AMD use different materials now.
Siegle: Yes, IBM uses SiLK, a spin-on, and we use a CVD material. We have been on a different path, but in our preliminary meetings with IBM we have had some healthy initial exchanges on low-k. There are, so to speak, many paths to Rome, to a reduced dielectric. We have put a low-k CVD dielectric in at Dresden for 130-nm going to 90-nm, and IBM believes they have their arms around the issues with SiLK.
We may end up doing a hybrid of CVD and spin-on. It's another open chapter relative to 65-nm, and we will be jointly figuring out the smartest thing to do.
EET: Besides low-k, what does AMD bring to the party?
Siegle: IBM and AMD both have a shortage of good engineers to work these issues, so they are more than anxious for the 40-to-50 engineers we envision putting in at East Fishkill N.Y., where the joint development work will be based.
Also, we have driven progressive implementation of manufacturing improvements, a continuous improvement in the manufacturing capability, that represents more rapid change than you would find in an IBM fab. It's a methodology that makes performance improvements very frequently, with small improvements. Most people don't do that. Most introduce larger changes every six to nine months. We have evolved a method to do that more frequently, making smaller changes.
EET: Do you mean thinning the gate oxide, or shrinking the design rules?
Siegle: It's that, and a whole laundry list of knobs.
EET: It seems a logical or natural thing to work with IBM at their new 300-mm fab. Are you talking about that?
Siegle: It does, as you said, seem almost a logical thing, and we are looking at that. We are in the process of examining what the appropriate 300-mm strategy will be for us. Almost certainly it will be a partnering strategy, based on the economics of what it takes to fill a fab. There frankly are several attractive options that we are considering. One is an extension of the IBM relationship. But that decision is not one that we are going to make hurriedly. We are going to spend several more months scrubbing out those possible paths.
EET: When does 300-mm become compelling in terms of costs?
Siegle: It becomes compelling when you can't buy leading-edge tools anymore for 200-mm wafers. With the industry slump that is not going to happen at the 65-nm node. And secondly, it is compelling when for a square inch of silicon, the cost of the finished wafer out of a new 300-mm fab compares favorably with the cost of a 200-mm wafer coming out of a partially depreciated 200-mm fab. Probably sometime between the 65-nm and 45-nm nodes, 300-mm becomes compelling.
EET: Can we conclude that AMD and UMC United Microelectronics Corp. won't build a joint fab in Singapore?
Siegle: In principle, Singapore is one of the options, but it would have to be considered a lower-likelihood option. That would have to be rationalized with UMC's own need for capacity. They have an operating 300-mm fab in Taiwan that is nowhere near full at this point in time. That's a contributing factor demand and loading at each of the companies become part of the equation.
EET: Why did AMD end its process development agreement with UMC?
Siegle: We mutually agreed we ought to disengage the joint development process that we had started to put together. A lot of things have changed just over a year's time. The economy has put both of us under considerable pressures.
To meet our technical requirements they would have to invest more heavily than the vast majority of their business would normally require. The conclusion we reached is that it was in both companies' best interest to find another way for us to get this leading-edge microprocessor work done.
This loops back to the point that the IBM product requires the same go-for-broke technology that we do.