MONTEREY, Calif.Volume production of 90nm designs will emerge in 2004 but the hurdles to get there are still significant, a panel of executives said Monday (Feb. 24).
The panel, assembled for a meeting of global electronics journalists here and chaired by EE Times senior editor Ron Wilson, navigated through the many pitfalls of ultra-deep submicron design and manufacture.
Pressed, panelists Ted Vucurevich, senior vice president with Cadence Design Systems, and Antun Domic, senior vice president and general manager of nanometer operations with Synopsys, agreed that designs would start ramping next year. Vucurevich said it would come in the form of an FPGA, while Domic said it would come in the form of a "non-FPGA" design, to which the audience chuckled.
The panel, aside from the light-hearted jousting over timing, did split over the treacheries ahead in the shift to 90nm design.
"The hurdles to getting to lower cost seem much different at 90nm" than for previous generational transitions, Vucurevich said. For instance, the cost to develop an advanced SOC is estimated at least $25 million and a year's design time, compared with a typical ASIC design ($300,000-$500,000), he added.
In addition, the costs of packaging a 90nm design could be more expensive than the silicon itself, Vucurevich said. "You're going to have to find new ways of verifying your design," he said.
Tougher than some think
But Domic countered that he believed the shift to 130nm from 180nm was far more difficult than this transition will be. In the earlier transition, the industry had to deal with the introduction of copper as a wiring choice and new dielectrics to handle the tighter geometries.
"Getting yields on that proved harder than expected," he said.
Andrew Moore, design services marketing manager with foundry TSMC, chimed in that the tools issues are different this time around. "The things at 130nm that were nice to haves are must-haves at 90nm," he said, noting that modeling of gate currents and SRAM redundancy contingency plans are imperative.
"There is a great deal of concern over variables," said Tim Burks, vice president of product engineering at Magma Design. "People are definitely concerned about low yields."
Vucurevich said manufacturing issues are increasingly global in that, for instance, designs need to fret about clock skew over multiple interconnects. But over time, local issues will also weigh heavy on the manufacturing side.
"Think globally and fear locally, then," Wilson quipped.