MUNICH, Germany -- Mask set costs of $20 million was a possibility used, like a bogeyman, to strike fear into the hearts of an audience for a panel session conducted on the floor at the Design Automation and Test Europe exhibition.
The panel, sponsored by the X Initiative, was subtitled 'Bridging the design to manufacturing gap' and was clearly orchestrated to try and raise awareness of design-for-manufacturability (DFM) issues.
Ken Rygler of Rygler Associates moderated the session and pointed out that in this year's DATE conference program there are no papers schduled on DFM but instead an emphasis on designs at a higher level of abstraction that might never be economically manufacturable.
It was also Rygler, fresh from attending the SPIE Microlithography conference in Santa Clara, who pointed out that write times for masks are increasing exponentially along with re-spins with each successive process technology node, and that if current trends continue unchecked, the total mask cost to produce a successful design in 70-nanometer process technology could reach $20 million per chip.
If the numbers seem extreme and Rygler later said that he doubted they would reach such levels. "Engineers love to extrapolate but that's what could happen if we do nothing. In other words something has to be done."
Simon Segars, executive vice president of engineering at ARM, started by playing the traditional role of the reluctant design engineer who has little interest in DFM, but Segars went on to acknowledged that although manufacturing issues should be taken care of by EDA tools, ultimately ARM is impacted if ARM-cored chips do not work first time or do not yield well.
"Models must be accurate or very safe, but safe leaves performance on the table," said Segars admitting that ARM-developed hard cores are sometimes 10% larger in area than finely tuned versions of the same cores developed by their licensees. This is the case because ARM needs to be able to port between processes quickly and needs to offer ease of manufacturability, Segars said.
Jean-Pierre, Schoellkopf, used the opportunity of the panel to announce that STMicroelectronics had successfully manufactured test-chips using 45 degree orientation on its 130-nanometer process technology, as part of its involvement in the X Initiative. Aki Fujimura, general manager of design for manufacturing at Cadence Design Systems Inc., said that this progress from STMicroelectronics is a major step after two years of hard work within the X-Initiative.
The use of the diagonal directions as well as 'Manhattan' rules is expected to allow die area savings of around 20% versus Manhattan-only designs.
Having produced 59 working test chips Schoellkopf said: "We are pretty confident this is going to work. But yield is yet to be confirmed."
While such progress within the X-Initiative might seem like good news, compensating for the some of the die area that ARM and others using up by their conservatism, it does not yet address the issue of right first time design.
While this was adopted as a mantra of ASIC design in the 1980s and 1990s the problems of design for manufacturing are resurfacing. Fujimura quoted number from Collett Research that show that 48% of chips fail first time and 20% fail on the first re-spin.
Riko Radojcic, director of business development at PDF Solutions Inc., latched on to this to point out that as technology complexity increases the skills gap is widening and rising development costs have squeezed out any possibility of iterative engineering.
Radojcic called for yield to modelled in simulation in a manner similar to area, power consumption and to be traded off against these parameters. "Yield must be quantified to be optimised. We need granular yield models," he said making the contrast with the rather simplistic design rules currently passed back from manufacturers to designers.
It was left to the last panelist, Steve Schulz, president and chief executive officer of the Si2 consortium to offer some solace, but also some prospective hardwork for the panelists.
Schulz, said that building on the success of Si2's Open Access database and the Oasis, chip layout information initiatives, Si2 intends to work with the Semicinductor Equipment and Materials International (SEMI) and Sematech to build extensions to Open Access to allow more of the designers intent to be passed forward to manufacturing.
"Open Access version 2.0 code is gaining adoption now. The next phase is to build on that in something called OA-UDM," said Schulz. "SEMI came up with this universal data model and we have this extensibility built into the OA database. So we are going to add UDM extensions to OA in partnership between Si2 and SEMI."
Questions from the floor revealed some vagueness of the definition of "manufacturability" among the panelists although consensus was eventually reached that it was probably design-specific. Questions also revealed the essentially iterative, chicken versus egg, nature of producing design rules to allow chips to be produce to test and develop the design rules.
A further question from the floor wrestled with the problem that for some designers, removed from manufacturing, the defect rates and yield numbers remain inaccessible.
The consensus on the panel was that manufacturability is a problem of increasing urgency that requires more collaboration between the different disciplines to agree information feed forward and feed back mechanisms. And the pain felt in manufacturing is almost certain to get worse before it gets better.