SAN JOSE -- Although it has not even ramped up its 90-nm process technology, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) here today (April 22, 2003) presented the first details of its 65-nm technology for use in next-generation designs starting in late 2004.
The baseline 65-nm process, of which TSMC calls Nexsys 65-nm Technology, will include copper-interconnects, low-k dielectrics, and high-k dielectrics. The process will also include options for strained-silicon and silicon-on-insulator (SOI) technologies to reduce power consumption for complex ICs.
Its 65-nm process is projected to move into "risk production"--or the qualification stage--as early as the fourth quarter of 2004, according to the company's roadmap issued at the TSMC 2003 Technology Symposium today.
A full-blown, system-on-a-chip (SoC) platform based on the 65-nm technology is slated for risk production in late 2005, said Jack Sun senior director of logic technology at the Hsinchu, Taiwan-based silicon foundry giant.
The company's 65-nm timetable is part of an overall effort to remain at or ahead of the two-year process technology cycle, as defined by the ITRS roadmap, Sun said. "We mean business," he said. "This is not just for bragging rights. We want to bring out the most advanced technology," he declared during a keynote address at the event.
TSMC is currently ramping up its 130-nm process, with plans to move into "risk production" with its 90-nm technology in the third quarter of this year. Its 90-nm process, also called Nexsys, will be in limited production this year, but will shift into mass production in 2004.
TSMC is also developing its 65-nm process. "We are in the process integration stage," Sun said.
Like its previous technologies, TSMC will offer three basic versions of its 65-nm process: general-purpose (CLN65G), low-power (CLN65LP), and high-speed (CLN65LV).
Enabling chips with gate densities of up 800,000-mm-square, TSMC's 65-nm process improves overall gate delays by 30 percent. The process will make use of copper-interconnects, as well as low-k dielectrics, with k values from 2.9- to 2.5.
Like its 90-nm process, TSMC will continue to use Applied Materials Inc.'s low-k offering, dubbed Black Diamond. Applied's low-k film is based on a chemical vapor deposition technology. Applied is working on a second-generation low-k material, dubbed Black Diamond II.
TSMC's roadmap also calls for the use of silicon dioxide as the gate dielectric in the first phase of the 65-nm node. But the company also plans to introduce high-k materials--that is, if some of the major barriers can be solved with the technology, Sun said. "There are still a lot challenges with high-k," he said.
The company will also introduce strain-silicon and SOI options at both the 90- and 65-nm nodes. Its strain-silicon offering is a "proprietary technology" that promises to reduce gate leakage by 14 percent, although Sun did not elaborate on the details.