BURLINGAME, Calif. - Frustrated with the integration issues of low-k dielectric materials, chip makers next week will present several novel approaches to the technology for 90-nm designs and below.
At the 2003 IEEE International Interconnect Technology Conference (IITC), Intel, Sony, TSMC, Toshiba, and other major chip maker will also present a sneak preview of their current and future low-k strategies. IITC runs from June 2-4 in Burlingame.
Japan's Toshiba Corp. and Sony Corp. will present one of the more widely anticipated papers at the event, entitled "Highly Reliable Cu/Low-k Dual-Damascene Interconnect Technology with Hybrid (PAE/SiOC) Dielectrics for 65nm-Node Performance eDRAM."
The embedded DRAM technology reportedly involves a combination of spin-on glass and chemical vapor deposition (CVD) low-k films. Both Toshiba and Sony have been using spin-on technology from Dow Chemical Co. in select products, but the Japanese companies may be seeking a hybrid approach in future designs, according to analysts.
Another possible futuristic approach is the use of air gaps as a low-k material. The team of Motorola Inc., Philips Semiconductors, and STMicroelectronics Inc. will present a paper, entitled: General Review of Issues and Perspectives for Advanced Copper Interconnections using Air-Gap as Ultra-Low-k Material."
On the 90-nm front, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) will present a paper on a porous film with a k value of 2.5--using a "novel" PEVCD technology. TSMC is using Applied Materials Inc.'s Black Diamond low-k film at the 90-nm node, but the silicon foundry giant is evaluating Black Diamond and Trikon Technologies Inc.'s Orion low-k technology at 65-nm, according to sources.
Intel Corp. will present a paper, entitled: "90nm Generation, 300mm Wafer Low k ILD/Cu Interconnect Technology." Intel is reported using a carbon-doped oxide low-k film from ASM International B.V. at the 90-nm node.