SAN JOSE, Calif. Andrew Kahng, a University of California-San Diego professor, brought to the Advanced Reticle Symposium here Tuesday (June 24) a warning, a call to action and a set of examples.
The warning was that increasing difficulty in producing cost-effective masks from chip design data could stall both the semiconductor and EDA industries in the near future.
The call to action stated that the chip design, EDA and process communities simply must cooperate to overcome these problems and maintain what Kahng called the cost trajectory of Moore's Law. In his examples, Kahng identified some low-hanging fruit: things that the three communities could work on at once to substantially reduce mask costs and improve yields.
Kahng said the industry needed a ''bi-directional design-manufacturing data pipe'' to convey data back and forth between chip design teams, mask makers and foundries. This pipe would pass design intent forward to mask makers, so that, for example, they could apply resolution-enhancement technologies only where they would improve post-test yield of dice.
In the reverse direction, Kahng's pipe would pass mask and process limitations back to design teams, so they wouldn't for instance insert mask correction features that couldn't be implemented or verified.
Kahng cited four examples. First, he said area fill and slottingtwo techniques for controlling the area and distribution of metal on the wafer to improve CMP uniformitywere not only significant in improving yield, but had significant electrical effects too. But he demonstrated that by sharing simple data between process and design teams, the impact of these techniques on routing and on electrical parameters could be sharply reduced.
Kahng also showed that if the tool that inserted OPC was aware of the actual timing requirements of the nets on which it was working, the amount of OPC features inserted could be dramatically reduced, with a very significant impact on mask cost. But this required passing netlist and timing data to the mask shop.
Kahng said a small amount of information about the mask writing equipment could greatly enhance the mask data preparation step. Finally, he illustrated taking the data pipe to the limit: an analog design in which there were, in effect, no design rules.
In this ideal world, analog designers had accurate models of the data preparation, resolution enhancement and lithography processes, so that they could optimize yieldand even such down-stream figures as project profitduring the optimization phase of analog design. In effect, designers would be working with models of the actual fabricated silicon structures during optimization, rather than with idealized device models.
Kahng suggested that a brute-force method of establishing communications between process and design teams was very likely to be imposed on the industry at the 65 nm node: highly restricted layouts, and possibly even prefabricated mask blanks that could only produce circuits cut from regular grating patterns. The researcher said his examples offered just a small sample from many readily available achievementsif only communication could be established.