SUNNYVALE, Calif -- How about error correction in embedded SRAM memory for free?
That's essentially what MoSys Inc. today announced with the launch of an enhanced single-transistor SRAM cell that combats a growing range of problems in manufacturing yields, chip reliability, and "soft error" rates as IC-design feature sizes shrink.
The new 0.13-micron 1T-SRAM-R memory macro adds what MoSys calls "Transparent Error Correction" to a new cell layout, which eliminates the 20% die-area penalty typically associated with error checking and correction (ECC) functions in traditional six-transistor SRAMS. In addition, the error correction feature does not impact memory performance, cycle patterns, or memory interfaces, said Andrea Hassan, vice president and general manager of memory products at MoSys.
The Sunnyvale-based company said the new higher reliability 1T-SRAM-R macro is now available for licensing. The memory macro is supported on standard logic processes, starting at the 0.13-micron generation at major silicon foundries, said MoSys.
A key target in development of the new 1T-SRAM-R macro was to address growing concerns about soft errors, which are caused by alpha particles and cosmic rays that bombard the earth. Energy from these particles can cause memory bits to change status, resulting in operational error of devices. In the 1980s, dynamic DRAM designers took action to fix the problem, but for the most part static SRAM memories were initially immune to soft errors. However that changes as feature sizes shrank and SRAM memory sizes increased.
"SRAM soft error rates are now actually getting worse by about an order of magnitude every generation," Hassan said.
Compared to traditional six-transistor SRAM designs, MoSys' existing 1T-SRAM cell offers lower soft error rates because of its smaller size and built-in redundancy. The small size of 1T-SRAM cells enabled chip developers to use standard logic design rules--avoiding aggressive feature shrinks--in the embedded memories, which helps to guard against soft errors. But now that logic feature sizes are reaching 0.13-micron and below, MoSys believes it's time to take corrective action with a new 1T-SRAM layout that further reduces the cell area without additional design-rule shrinks.
The new 1T-SRAM-R layout makes room for the "Transparent Error Correction" by reducing its size by 20%. The added error correction feature more than overcomes the potential for an increase in soft error rates (SER) due to the use of finer 0.13-micron feature sizes, according to Hassan.
"Reducing the cell size basically allows us to add ECC for 'free' while still staying within the standard design rules of 0.13-micron processes," he told SBN. "We are improving the soft error rate by a couple of orders of magnitude, taking it from 1,000 FITs failures in time per megabit at 200 MHz to roughly 10 FITs without increasing the size of the memory area."
MoSys said the new 1T-SRAM-R will pack a megabit of memory with error correction in 2 mm2 using 0.13-micron process design rules, while a six-transistor SRAM with ECC will take 5.5 mm2 to achieve the same level of soft error protection.
In addition to protection against soft errors in the field, the 1T-SRAM-R cell also helps to avoid the use of laser-repair steps in manufacturing, which lowers production costs and increases fab yields, according to MoSys.