FREMONT, Calif. -- ChipPAC Inc. here today announced it has qualified all the frontend assembly steps needed for the packaging of ICs from 300-mm diameter wafers, including new processes that will thin substrates to as little as 150 microns.
"Wafer thinning is the most critical of all operations because it determines the minimum package height possible in CSP chip-scale packaging and SiP system-in-packaging," said Marcos Karnezos, chief technology officer at ChipPAC. "Our 300-mm line can start with a 778-micron thick wafer and thin it to 150 microns by combining well-established mechanical back grinding and a new mechanical polishing without resorting to the costlier chemical or plasma etching technologies less common in packaging assembly operations.
"We are also on track to further reduce wafer thickness on 300-mm wafers to 100-125 microns by the second quarter of this year, which will match our current capabilities in 200-mm and allow us to continue to offer the industry's thinnest CSP and SiP package families," he added.
The supplier of IC assembly and testing services said it has developed a proprietary polishing process that relieves the accumulated stress from back-grinding of 300-mm wafers. This new process step is "critical to our ability to reach 100 microns or less in processing 300-mm wafers," Karnezos said. The thinning of larger diameter wafers presents additional challenges for assembly plants because of an increased risk in breakage. Larger 300-mm wafer often bow while substrates are handled.