SANTA CLARA, Calif. -- Integrated Device Technology Inc. today announced the industry's first FIFO memory chips with high-speed double-data rate (DDR) interfaces for clock frequencies up to 250 MHz and data rates up to 40 gigabits per second.
The new TeraSync DDR first-in, first-out chips have been optimized for Sonet equipment, Fibre Channel links, Gigabit Ethernet networks, imaging processing products, instruments, and other high-speed systems applications, according to IDT here. The DDR FIFO series more than doubles the bandwidth currently available for high-speed systems in enterprise and carrier-class networks, IDT said.
In addition to the DDR interface, the new FIFOs contain advanced features for fast systems, including mark and retransmit, echo clock and enable outputs, read chip select and JTAG-based I/O, said Mario Montana, director of FIFO products at IDT. The DDR FIFOs have up to 5-megabit of memory in by-40, by-20, and by-10-bit configurations.
With the DDR interface, a 250-MHz clock cycle will produce 500-Mbit/sec. data rates per pin. The FIFOs are packaged in a 208-contact ball-grid array (BGA) and available with user-selectable HSTL or LVTTL input-output levels, said the company.
"By going to double-data rate, you can save pins if you are trying to double the throughput without going to a wider bus, or you can relax the speed of the fundamental clock rate," Montana told SBN.
"The challenge with any high-speed FIFO is managing the asynchronous clock domains of the interfaces and latching data in the memory in a predictive manner," he added. IDT has developed innovative structures in the devices to deal with the 250-MHz clock speeds and DDR interfaces.
"We have a quad-port internal cache, where the data is written in at a very high speed and there is a widening of the data path internally to a slower memory core. That allows us to pack in a lot of density in the die area," Montana said.
The new TeraSync DDR FIFOs are fabricated with IDT's 0.18-micron CMOS technology, which has been "memory tuned." The core voltage of the FIFOs is 2.5 V. Samples are available now with volume shipments starting in April.
Volume prices for the DDR FIFOs start at $37.74 each (16-Kbit-by-40) in 10,000-unit quantities. A DDR 5-Mbit FIFO configured 256-Kbit-by-20 or 512-Kbit-by-10 sells for $64.26 each in quantities of 10,000.
--J. Robert Lineback