SANTA CLARA, Calif. -- During a series of presentations here this week, Agilent Technologies Inc. gave a sneak preview of plans to upgrade its IC testers for cutting-edge communications semiconductors, system-on-a-chip products and other devices.
Agilent is expected to officially announce the upgrades at the Semicon West trade show in San Jose during July 17-19. But at a company conference on Wednesday, the Agilent disclosed its 93000 eXtended Platform--a concept that promises to support and test ICs at speeds of 10-gigabits per second and beyond, according to officials.
The company said it also plans to integrate a new version of its "test processor" into the existing 93000 line of SoC testers, which will double the digital pin-count on the system from 1,024 to 2,048 channels. The "test processor" is a chip-level ASIC inside the 93000 tester.
Meanwhile, Agilent's eXtended Platform includes two new major upgrades to its 9300 tester. Launched in 1999, Agilent's 93000 line of automatic test equipment (ATE) is a 1,024-pin system that supports data rates up to 1.25 gigabits per second.
The new upgrades will address all requirements for testing chips in Ten Gigabit Ethernet and other high-speed networks, said Markus Knoch, an applications consultant for Agilent, during Wednesday's presentation.
In fact, the company is planning two new major upgrades for the 93000, dubbed XP3G and XP10G. Both of these products involve a move to integrate Agilent's standalone 81250ParBERT line of parallel bit error ratio test platforms within the 93000.
As a result, the XP3G upgrade will enable the 93000 to support up to 64 native differential channels and a data rate of up to 3.3-Gbit/second, according to the company.
Meanwhile, the XP10G upgrade will enable the 93000 to support up to 8 native differential channels at speeds up to 10-Gbit/sec. The XP3G upgrade will be available in May, while the XP10G will be offered in the fourth quarter, according to Knoch.
In a separate move, Agilent plans to implement a series of die shrinks for the "test processor" within the 93000. The "test processor" enables the 93000 to support a tester-per-pin architecture at fast data rates.
The "test processor" within the 93000 is a 0.35-micron ASIC right now, but the company plans to shrink the chip to 0.25- and 0.12-micron die sizes in the future, said Yih-Neng Lee, vice president and general manager of Agilent's worldwide fabless design house business. The move would enable the 93000 to support 2,048 pins, up from its current 1,024 channels, Lee said during a presentation.
In an interview with SBN after the presentation, Lee said that Agilent is gaining momentum and market share in the ATE business in spite of the downturn in the semiconductor industry.
The company is also growing faster than its ATE rivals, Lee said. "We think Agilent is in a better position than our competitors," he said.
He added that Agilent is seeing growth in the test subcontractor community in Asia. "Today, most of the ATE activity is in Asia," he said. "The IDMs are still slow in obtaining new ATE," he said.