AUSTIN, Texas Progress reports at this year's VLSI Symposia on Technology and Circuits in Hawaii are expected to describe a gaggle of companies racing to develop 100-nanometer silicon processes and circuits that take advantage of today's 130-nanometer technology node.
The papers are scheduled for delivery in June at two separate symposiums on very large-scale integration technology and circuits to be held at the Hilton Hawaiian Village in Honolulu. The presentations will be supplemented by day-long workshops on sub-70-nm process technologies and low-leakage circuits.
In the technology session held June 11-13, IBM Corp., Fujitsu Ltd., Motorola Inc. and NEC Corp. will roll out 100-nm process integration strategies, describing their approaches to multithreshold voltages, multigate oxide thicknesses, gate oxides and intermetal dielectrics.
Fujitsu, for example, will describe a 100-nm CMOS technology that combines copper interconnects and the SiLK low-k dielectric material from Dow Chemical Corp. The SRAM cell size reported by Fujitsu is 0.999 square microns. Mitsubishi Electric goes that slightly better, describing a 0.998-micron2 SRAM cell size.
Taiwan Semiconductor Manufacturing Co., which has used chemical vapor deposition (CVD) low-k dielectrics for its high-performance 0.13-micron technology, will describe a spin-on dielectric with a k-value of 2.2 that is being evaluated for its 100-nm and 70-nm processes.
Ken Rim from IBM Corp.'s T.J. Watson Research Center will describe the process integration of strained silicon which takes advantage of the pull that germanium atoms exert on a thin top layer of silicon and high-k gate dielectrics. IBM claims that the hafnium oxide HfO2 gate insulator reduces leakage by three orders of magnitude. To counter the slower mobility often seen with high-k gate insulators, IBM researchers will use transistors built on strained silicon, which improves mobility by 30 percent compared with conventional silicon NMOSFETs that use silicon dioxide gate dielectrics.
Japan's Advanced Super Electronics Technology (ASET) research consortium also will report its work on strained silicon technology.
Several U.S. and Japanese companies will describe progress with hafnium oxide and hafnium silicate dielectrics. Motorola has evaluated several metal gates integrated with HfO2 dielectrics, and will present performance evaluations of the combinations.
The circuits meeting, scheduled for June 13-15, includes an Intel Corp. presentation on a Pentium 4 processor running at 3 GHz, based on a 130-nm process with 70-nm gate lengths. The integer unit operates at double the clock frequency, or 6 GHz, in a chip that makes extensive use of low Vt (threshold voltage) transistors to speed up the critical paths.
Parallel reading and writing
IBM will describe an embedded DRAM technology that circuits program committee member Wai Lee of Texas Instruments said will reduce access time to just 2.9 nanoseconds, compared with 6 ns typically. The circuit is based on a 130-nm (0.13-micron) process. By postponing the write-back operation and performing it in parallel with a read operation, the IBM eDRAM presentation "by itself may trigger more interest" in combining logic and embedded memory, said Lee.
Samsung Electronics engineers will present a 32-Mbit ferroelectric RAM, the first reported to achieve that density. Another Samsung group will describe a sub-100-nm DRAM process built around a RuTa2O5 (ruthenium tantalum pentaoxide) capacitor, and a Hynix Semiconductor team will present its gigabit DRAM technology.
Several extremely fast interface circuits will be described, including a Rambus Inc. CMOS quad serial transceiver that ranges from 400 Mbits/second to 4 Gbits/s, implemented in a 0.13-micron technology. It includes an on-chip voltage regulator that minimizes noise from the nearby digital circuits.
NEC engineers came up with 5-Gbit/s transceiver, also done in 0.13-micron CMOS, which includes a continuous-time post equalizer circuit with high-speed analog amplifiers.
Lee said it is getting harder to transmit signals from chip-to-chip at speeds that approximate the microprocessors now coming to the market. "It requires very good analog design to create these transceivers in a regular logic process. Those circuits represent quite an achievement," said Lee, the symposiums' publicity chairman.
The evening panel sessions will include debates on:
The merits of system-on-chip integration vs. the system-in-package approach;
Whether the industry really needs a new MOSFET structure;
What memory technology will follow flash and DRAMs;
Whether 157-nm lithography will arrive on time, or whether the industry will go directly to extreme ultraviolet scanners;
How to deliver good-performance analog in the increasingly low-power-supply digital CMOS processes.