HOUSTON -- Texas Instruments Inc. today announced it has expanded the scope of its TMS320C64x series of digital signal processors to address low-power consuming applications with a DSP chip that cuts the cost of multiply/accumulate functions in half, compared to its nearest competitors.
The new 320C6411 processor runs at 300 MHz and handles 2,400 millions of instructions per second (MIPs), which in turn executes up to 1,200 million multiply/accumulates per second (MMACS). TI said the processor will be available for $39 each in 10,000-unit quantities.
The C6411 is aimed at such applications as residential media servers, security/surveillance systems, telecom/datacom systems and hardcopy appliances. The new 0.13-micron CMOS processor is based on a C64x DSP core that is already addressing high-performance, multi-channel applications in networking and communications infrastructure. The C6411 has been given a number of features to emphasize lower power consumption and costs while handling fewer channels.
The move is part of TI's strategy to match new DSP designs to a range of requirements in embedded applications, said Yvonne Cager, marketing manager for the TMS320C6000 DSP series based in Houston. "The C6411 DSP cuts the dollar-per-mega MAC by as much as two times, and it lowers the milliwatts-per-MMAC by as much as 50%," she told SBN in an interview.
TI has added features to the C6411 to address various low-power, low-cost applications, while still delivering needed DSP performance. For example, the new processor has 8-bit hardware extensions to dramatically improve video and image processing applications in residential media servers, said Jackie Brenner, a member of the technical staff and C6000 architecture team at TI. "The C6411 can execute eight instructions every clock cycle. So, 300 MHz is 2,400 MIPS," she said.
In addition, bit-count and bit-rotate hardware in on the C6411 to enable faster pattern matching, which can be used in security systems that employ iris scanners to identify people by their eyes. "This technology allows scans of 250 independent variables," Brenner said. "By contrast, fingerprint verification systems typically scan only 80 variables."
TI also claims its C compiler outperforms those offered by Analog Devices Inc. and Motorola Inc. on 300-MHz DSPs. In a JPEG encoder/decoder benchmark applications, the C6411 can handle compression/decompression of images in 816,000 cycles, while code for Analog Devices' 21535 "Blackfin" DSP uses over 5.6 million cycles and Motorola's MSC8101 (StarCore) takes 5.2 million cycles to perform the function, said TI's Cager. The power consumption of the C6411 is also one-tenth of the DSPs from Analog Devices and Motorola, she added.
Samples of the C6411, packaged in 532-contact ball-grid arrays (BGAs), will be available in the third quarter with production volumes beginning in the fourth quarter.