TOKYO -- In a move to create a new class of ASIC products for "mid-volume" applications, NEC Corp. today introduced a functional-block chip architecture, which allows customers to quickly route pre-existing cells on ICs for custom designs using two upper layers of metal--just like a gate array.
NEC's new type of application-specific ICs are called "Instant Silicon Solution Platforms" (ISSPs), and they are targeted at ASIC designs with expected market volumes of a few thousand to 100,000 units.
The company believes that the growing cost of custom IC photomasks and increasing complexities in chip development cycles are driving the need for a new mid-volume ASIC solution. Photomask costs for new IC designs are now pushing towards $1 million per reticle set. At the same time, NEC does not believe that programmable logic devices are able to keep up with the performance requirements in a growing number of systems applications.
NEC said its new ISSP architecture will offer up to 75% reduction in development and production turnaround times compared to regular standard cell-based ASICs. The non-recurring engineering (NRE) costs are also expected to be reduced by up to 10 times compared to cell-based IC designs, said the company.
"At this point, there is nothing like it on the market," said Sudhir Mallya, senior manager for the LSI Systems Business Unit of NEC Electronics Inc., the Santa Clara, Calif.-based chip unit of the company.
The ISSP series starts off with a standard embedded core series of SRAM blocks and multi-function phase-locked loop (PLL) blocks. NEC will also offer "system-level integrations" ISSP chips with SRAM, PLL and embedded processors cores. A high-speed interface ISSP series is also planned, which adds functions for a range of communications and networking applications, such as serializer/deserializer (Serdes).
The standard ISSP products will become available in the third quarter. These products will be fabricated with 0.13-micron CMOS technology, similar to NEC's standard cell-based process but with five-levels of aluminum metal interconnect. The last two layers of metal are used to customize the embedded cells for ASIC designs.
"The time from when a customer give us a completed design to the time they receive samples could be three to four weeks," said Mallya in a phone interview. "Standard cell-based designs could take months before devices are delivered," he added.
NEC's ISSP architecture packs a number of features, including embedded clock domains, testing technology (such as boundary scan and built-in self test, or BIST), and complex multi-gate functions that can be customized with two layers of metal. The company believes it has combined the best features of cell-based and gate arrays to offer short design cycles with higher performance than field programmable gate arrays (FPGAs), Mallya told SBN.
The ISSP non-recurring engineering cost will be in the $50,000-to-$100,000 range, compared to an NRE of $500,000-to-$1 million for Cell-based ICs, he said. FPGA typically have an NRE cost of about $5,000-to-$10,000, but they are more suitable for lower production volumes, and often performance limitations prevent them from being used in 200-MHz and above applications, according to Mallya. He also said FPGAs are now limited to less than 1 million usable 'ASIC gates,' while the initial standard ISSPs will have up to 1.1 million gates.
Operating with system clock speeds of up to 300 MHz and local clock speeds of 400 MHz, the first ISSP devices will have up to 60,000 internal registers and up to 1 megabits of embedded configurable memory. The products will operate with an internal supply voltage of 1.5 volts and interface to 2.5 volts and 3.3 volts input/output sources. NEC said the ISSP chips will have an internal power consumption of 0.014 microwatts per MHz per gate.
--J. Robert Lineback reporting from the U.S.