PALO ALTO, Calif.--Agilent Technologies Inc. today announced the first single-chip solution for Gigabit Ethernet over Sonet and Synchronous Digital Hierarchy (SDH) networks. The Ethernet-over-Sonet (EoS) mapper chip integrates a serializer/deserializer (SerDes), clock data recovery and OC-3 to OC-48 framer functions, Agilent said.
The HDMP-3002 is the second member of Agilent's multi-protocol IC family. These MPIC devices take protocol independent traffic and map it into Sonet/SDH. Agilent said the chip provides a simple solution for loading enterprise data traffic onto Sonet/SDH metro infrastructure systems.
"Agilent's new EoS mapper chip significantly reduces the cost of transporting enterprise data over the legacy Sonet/SDH infrastructure, satisfying the needs of corporate users and service providers," said Philip Gadd, IC marketing manager for Agilent's ASSP Products Division.
The HDMP-3002 provides full-duplex mapping of Fast Ethernet and Gigabit Ethernet frames encapsulated into STS-48/12/3 Sonet/SDH payload using the generic framing procedures (GFP), frame delineated HDLC (per RFC 1662/2615), or the link access procedure-SDH (LAPS) protocol. The device can connect up to four Gigabit Ethernet feeds into one STS-48/STM-16 (2.488 Gb/s), four STS-12/STM-4 (622 Mb/s), or four STS-3/STM-1 (155 Mb/s) channels, Agilent said.
The mapper chip is a layer-2 solution implemented in a low-power 0.18-micron CMOS process with a 1.8-volt core and 2.5- and 3.3-V I/Os. The device is housed in a 664-contact ceramic ball grid array (CBGA) package and supports the OC-48/STM-16 (2.5 Gb/s) standard.
Agilent said it is now shipping samples of the HDMP-3002 mapper device to selected network equipment manufacturers. It is priced at $475 in 1,000-unit quantities.