ORLANDO, Fla. The pace of CMOS scaling may slow over the rest of this decade as leaky transistors and interconnect problems become more intractable, and the technology may run out of gas by 2012, according to technologists at the Custom Integrated Circuits Conference here. And whatever is to replace CMOS must be invented now, because it will take at least a decade to develop into a commercial technology, speakers said.
But the vexing issue for IC designers at present is rising mask costs. At 0.13-micron design rules, a mask set can cost up to three times more than a 0.18-micron mask set.
"Mask costs are killing us," said one engineer at a panel on CMOS scaling. "If it cost $600,000 to do a respin, we just can't afford that if it's a small design team like mine. We have to have silicon to get a design win from a customer, and not many companies can afford to spend another $600,000 to respin a mask set when you don't even have a design win yet."
High mask costs are an even bigger problem for universities, Brian Ackland, vice president of circuit and systems research at Agere Systems (Holmdel, N.J.). "University research teams just can't afford to take a design to silicon when mask sets are so expensive," he said. "It is having a big impact in industry, but making a mask set is getting to be out of reach for university researchers."
Prototyping services available from silicon foundries offer some relief to small design teams, but even companies that operate their own fabrication facilities are moving some designs to foundries to take advantage of the "silicon shuttle" approach, in which a foundry puts multiple IC prototypes on a single mask set. Taiwan Semiconductor Manufacturing Co., for example, allows a design team to buy a 5 x 5-mm square of a 0.13-micron wafer for about $75,000 to test out a design and get enough prototypes to approach potential customers, said a Motorola Inc. engineer at CICC.
Dennis Buss, vice president of silicon technology development at Texas Instruments Inc., agreed that mask costs are a problem for small design teams. For a TI standard product, which can distribute mask costs over high volumes, mask costs have not yet become prohibitive, Buss said. Halving a die size by going from 0.18-micron to 0.13-micron design rules, for example, makes the move to a more expensive mask set worthwhile for TI's volume products, he said.
Power consumption is another problem that is not getting sufficient attention, members of the CICC panel agreed.
More research is needed to reduce wasted power, particularly the sub-threshold leakage when devices are in the off state. "The CAD community is really not doing anything" to develop research tools that would help deal with the transistor leakage problem, said Intel Corp. fellow Shekhar Borkar. Purdue University professor Roy Kaushik is one of the few academics to have worked on the transistor leakage problem from the CAD perspective, Borkar said.
Beyond that, little basic research is being done within universities. "The CAD community is not helping us," Borkar said.
End seen for double-gate structures
Buss said CMOS scaling will continue to offer performance, density and cost advantages for the next decade, but that CMOS will run out of steam by 2012 when gate lengths are at 10 nanometers, or 0.01 microns. "By CMOS, I include all of the double-gate structures," he said. "My guess is that by then we will be using a dual-gate FinFET," he said.
But whatever technology is to take the place of the venerable MOSFET be it molecular structures, carbon nanotubes, MEMS, or other next-generation technologies must be invented now and developed full-bore over the next decade in order to be ready in time, Buss said.
Today's 130-nm processes use a 65-nm gate length, and gate lengths will shrink to 45 nm or so by next year when 90-nm design rules are first introduced, Buss said. "The end of the road map for CMOS is coming upon us much sooner than we think," he said.
Stanford University professor Krishna Saraswat said that by the 70-nm node, expected in 2005 or 2006, "we are running out of steam and will need to make changes in the materials and structures." The combination of high-k gate insulators, fully depleted SOI, and strained silicon will help keep performance scaling somewhat on track, he said. However, Saraswat warned that interconnect delays will become much worse. "Copper which poisons silicon needs barriers, and that will cause resistivities to increase," he said, pointing to optical or wireless interconnects as possible long-term solutions.
Also, the industry must put more funding into 3-D structures, in which logic devices, memory, sensors, and chip-to-chip optical interconnects would be stacked and connected vertically in a single package.
Saraswat pointed to two research efforts that could replace CMOS. Benzene-based molecular devices have been developed at Lucent Technologies that show excellent properties, though he noted that the results are preliminary and have not been duplicated elsewhere. And carbon nanotubes that use free space as the gate have been the subject of promising research at the University of California at Berkeley.