HONOLULU With the transition to copper and low-k interconnects showing just how difficult changes in materials can be, technologists gathered at the 2002 Symposium on VLSI Technology here last week to consider a brace of materials challenges ranging from new gate oxides to SOI and strained-silicon channels.
Experts said at least four or five more transitions are coming. High-k gate insulators will be needed to replace silicon dioxide, metal gate electrodes will replace polysilicon, and silicon-on-insulator (SOI) and strained silicon may be needed to improve current drive. And during the next decade, planar CMOS could give way to vertical dual-gate structures, such as the FinFet structure proposed by Chenming Calvin Hu, the chief technology officer at Taiwan Semiconductor Manufacturing Co. Ltd.
Taken together, the materials transitions promise a period of upheaval that will rival the early 1980s, which ushered in CMOS circuit design.
While IBM Corp. pushes SOI and plans to introduce strained silicon as soon as the 65-nanometer node in 2005-2006, Intel Corp. remains unconvinced about SOI as well as strained silicon. Last December, Intel researchers went to the 2001 International Electron Devices Meeting armed with a fully depleted SOI approach, which Intel calls depleted substrate transistors (DST), that it said would enable a terahertz transistor.
Asked if Intel has definite plans to introduce DST, Mark Bohr, in charge of Intel's process technology development, said, "I can't say that we do. It is very clear that partially depleted SOI which IBM now uses for its leading-edge processors has no value. And there are still unanswered questions" about fully depleted SOI.
"We do see with DST a steeper sub-threshold slope: For a given on-current there is a lower off-current. But that technology requires SOI wafers with a top silicon layer that is 10 nm to 15 nm thin. We may have a steep sub-threshold slope, but in such thin silicon there may be added parasitic resistance in the source and drain regions, so we may not get all of that current gain.
"And then there is the wafer availability question. All in all, we are still considering whether DFT is a step that will be worth the price. It is competing against bulk," Bohr said.
IBM Microelectronics' chief technology strategist Bijan Davari took a polar opposite view, declaring that IBM plans to introduce strained silicon technology at the 65-nm node for its highest-performance products. Strained silicon on SOI (SSOI) will be needed to boost performance and to compensate for the mobility degradation caused by high-k gate oxides, Davari told EE Times before the VLSI meeting.
With a strategy of bringing SSOI to products within the next five years, IBM promises to pioneer another daunting technology, as it did with copper, low-k dielectrics, and partially depleted SOI. Intel and Texas Instruments Inc. plan to introduce a high-k gate dielectric at the 65-nm node. But Davari said he thinks strained silicon will be introduced to IBM's fabs before the transition to a high-k gate material.
"High-k is a very tough problem. People have started working on it, but not enough attention has been paid to it. Silicon dioxide is this amazing material; the interface with silicon is so good it will take more time to develop alternatives. For high-k to be effective, it almost certainly needs some other gate material than the polysilicon electrode, otherwise the poly depletion will kill it. For the electrode function, we may need to go to dual metal gate electrodes at the same time we introduce a high-k gate.
"In my opinion, this road map strained silicon before, or at the same time, as a high-k gate dielectric must be followed. If you don't have SOI and strained silicon, if you don't have a high-k gate material to prevent leakage, then you can't get any benefits from shrinking" other than higher transistor densities.
Dimitri Antoniadis, the MIT professor who has pioneered research in strained silicon and SOI technologies, warned of "very significant issues as we ramp up new materials. We may know how to make something like SOI or strained silicon, but can we make it in huge volumes? Will the wafers be available? Some things, like SOI, could come in very fast. But will the manufacturers have the confidence that the materials will be there in the volumes that would be needed?"
IBM researchers put strained silicon long the subject of active research at MIT and Stanford on center stage at last year's VLSI Symposium in Kyoto.
At last week's VLSI Symposium, Ken Rim, a research staff member at IBM's T.J. Watson Research Center, described progress on several fronts. IBM used ultrahigh-vacuum chemical vapor deposition equipment to grow a graded silicon-germanium buffer with a germanium content of 15 percent to 20 percent. A thin silicon layer was epitaxially grown on top of the relaxed SiGe layer. The larger SiGe atoms place a slight strain on the silicon lattice, allowing much higher electron mobility through the channel.
For reasons that are not well understood, hole mobility in the PFETs improves much less in strained silicon channels vs. dramatic gains in electron mobility in the NFETs.
Rim said strained silicon with a 13 percent germanium content resulted in a 15 percent boost in Ion in NFETs. At 28 percent germanium content, strained silicon PFETs showed a 7 to 10 percent performance improvement compared with bulk devices at 0.13-micron design rules. To achieve higher current drive improvements, a germanium content of about 35 percent is needed to boost hole mobility by 20 percent, Rim said.
Antoniadis said research on strained silicon at MIT indicates that a germanium content of 35 percent exerts the optimum level of strain on the active silicon layer, delivering electron and hole mobility enhancements of 75 to 80 percent, which translate into drive current improvements of about half that: 35 to 40 percent. But, to maintain the strain in the silicon layer at the level of 35 percent germanium, the active silicon layer must be thinned to 8-nm equivalent thickness.
"We can grow a thicker silicon layer and then thin it, without relaxing the strain. But as the germanium content increases, the critical thickness of the silicon layer must be thinner. A thicker silicon layer breaks under the strain, causing dislocations to the planar silicon structure," Antoniadis said.
Making wafers in volume with such delicate structures will be difficult. "There is no question that it is going to be hard, and questions are constantly being raised. But if we must continue to scale performance, this is one way to accomplish that. Now the industry may discover that it cannot afford it," Antoniadis said.
Questioned after his VLSI presentation last Wednesday (June 12), Rim acknowledged several challenges to making strained silicon work. The abrupt arsenic doping profile which is critical to good MOSFET performance is difficult to maintain because arsenic tends to move around in germanium. "The arsenic movement in silicon germanium causes a threshold voltage roll-off," Rim told one of many questioners after his presentation. Also, silicon germanium has thermal characteristics that cause self-heating in the silicon and silicon germanium structures: Rim reported a 100°C increase in the channel temperature compared with bulk.
Threading dislocations in the silicon lattice also pose a major challenge, affecting the threshold voltage of transistors sitting on top of a dislocation there are 10,000 to 100,000 of them per square centimeter in the active silicon layer. Rim said, "This is a critical issue, and we are working to optimize the material. And we need to understand better what these dislocations do. But there is no reason to be pessimistic about the prospects" for solving the materials challenges.
IBM is not the only company working on strained silicon. Fujitsu Ltd. researchers presented work here last week, as did a Toshiba Corp. team. And Hitachi Ltd. has an active program.
Japan's government-funded Aset program (Association of Super-Advanced Electronics Technology) is supporting a strained silicon research group from Toshiba, and other Japanese companies are likely to join the Aset effort as well. Shinichi Takagi, leader of the Toshiba team, said his group has come up with an oxidation method that condenses germanium into the graded SiGe layer.
The innovative approach created a strained silicon layer on an SOI substrate, with a minimum of threading dislocations compared with strained silicon on bulk silicon substrates. And while IBM's work at last week's conference was all about strained silicon on bulk wafers, Rim said his team's most promising work, under preparation for further disclosures, also is on SOI wafers.
Takagi's team claimed strained silicon CMOS bragging rights: Tomohisa Mizuno, another Toshiba researcher, presented the first published achievement of strained silicon CMOS, albeit at 0.5-micron design rules. (IBM used 0.13-micron design rules for discrete nMOS and pMOS devices, but has not integrated them into CMOS.)
Mizuno compared bulk CMOS performance with ring oscillators created in both partially depleted and fully depleted strained silicon SOI. The early results showed ring oscillator switching improved by about a third in the partially depleted SSOI over the bulk.
Takagi acknowledged that the half-micron design rules that his team used may not prove that much, saying it needs access to a better R&D fab in order to push the Toshiba SSOI technology to short-channel devices.
Intel's Bohr again handled the rebuttal with strained silicon, much as he has done with SOI.
"Strained silicon is not a new idea. But I have questions about whether the electron mobility enhancements are going to result in real transistor drive performance, which is the bottom line," Bohr said.
Noting that IBM reported a 15 percent gain in current drive for NMOS, and 7 to 10 percent gains in Ion in the pMOSFETs, Bohr argued that those levels of performance improvement over bulk CMOS remain unimpressive and may not stand up as strained silicon moves into devices made with leading-edge design rules.
"Ten years ago, university researchers also reported electron mobility enhancements and the question we have today is the same as then: Will these electron mobility enhancements in long-channel devices translate into improved drive current gain on state-of-the-art transistors?
"If there were 50 percent gains in drive current, and not in the range of 10 percent, there would be a benefit. I think we have to look really carefully at whether the performance improvements with strained silicon are going to be sufficient enough to implement the technology. To my mind, the issue is undecided."