AUSTIN, Texas IBM Corp. will describe a transistor-resizing tool at the 39th Design Automation Conference next week that could make manual, full-custom design a thing of the past. Big Blue is making some heady claims for the EinsTuner tool, which it uses internally on microprocessor designs and may eventually be applied to commercial ASICs as well.
By automatically resizing all of the transistors in a circuit, EinsTuner has improved microprocessor performance by about 15 percent, said Chandu Visweswariah, one of the developers of the tool. Over the past year and a half IBM has applied EinsTuner to its Freeway System 390 mainframe processor, the Regatta Power4 server processor and a low-power-consumption PowerPC controller, among others. It also is being used in the development of the Cell processors that IBM, Toshiba and Sony are co-designing for distributed-computing entertainment platforms.
Visweswariah will present a paper at DAC on how to coordinate EinsTuner with manufacturing techniques, so that variations in manufacturing can be taken into account when tuned circuits are used widely in a design.
For decades, microprocessor designers have resized transistors as part of full-custom design techniques, tweaking them by hand in arrays, muxes, register files and data flow stacks in critical circuits such as the instruction and execution units,leaving the rest of the design including random logic and cache memory to automated techniques.
"If humans tweaked forever, they would never get as good as EinsTuner," said Visweswariah, a researcher at IBM Research in Yorktown Heights, N.Y. "Besides delivering a better circuit, it enhances design productivity. Just make an appropriate schematic and give it to EinsTuner, and it does all of the work. It makes trade-offs at a higher level" than human designers.
Visweswariah spent several years working on sensitivity, the field of design automation that looks at how circuit performance shifts based on small changes to the circuit parameters. Pinpointing improvements that he thought would draw raves from IBM designers, Visweswariah found instead that "nobody cared."
So he and several other staff members at the Watson Research Lab set out to integrate the work into a more-complete design loop, including the key simulation and timing steps. After more than a year of work, Visweswariah, mathematician Andy Conn and colleagues Greg Northrop and Phil Strenski had a working prototype that was tried out on several designs.
To develop a production-worthy tool, six other IBM EDA engineers developed EinsTuner. The tool is integrated with the other "Eins" tools used within IBM, such as the EinsTLT static transistor-level timing tool upon which it is built. EinsTLT combines an event-driven simulator with the EinsTimer tool.
Through a graphical user interface, users input the desired parameters of a design, giving weights to performance, die size efficiency, power consumption and other factors. EinsTuner's algorithms "take all of these trade-offs and find the optimum sizing for all the transistors within a circuit," Visweswariah said. "It decides if a transistor should be wider or less wide, and takes into account all of the millions of paths within those transistors. This shifts the designer's thinking to a higher level."
By implicitly considering all of the potential paths, Eins-Tuner can process a 20,000-transistor circuit in about six hours on an engineering workstation. "By the cleverness of the formulation, mathematical trickery if you will, we get the same coverage as if we had mechanically listed all of the paths," Visweswariah said.
Because the algorithms are "eminently parallelizable," a future version of EinsTuner could be created for a parallel-processing machine, he said.
Visweswariah said EinsTuner can be applied to full-custom, semicustom and random-logic generation design techniques. In a full-custom design, a cell generator is used to create a custom cell, within the limits of manufacturing gradient tolerances of .05 micron or so. In semicustom designs, EinsTuner can choose among the variously sized primitives within a cell library and pick the optimum cell to meet a set of parameters constraining size, power and performance.
Visweswariah said that because EinsTuner works with custom, semicustom and synthesized random logic, there is no inherent reason why it could not be extended beyond microprocessors to more-general types of circuitry, including commercial ASICs.
"Now that we have this tool, there are a number of investigations going on within IBM about how we can extend this capability," he said. "This is like opening Pandora's box. We have spent the last year and a half using this on internal designs and improving on the prototype, and we are at a point now where we feel we can talk about it more openly."
Besides improving circuit performance by 15 percent, EinsTuner could have an equally dramatic impact on shrinking die sizes. It could be used to compress a design by a third or more, Visweswariah said.
"For 30 years, people in the industry have been working on the high-powered math needed to accomplish something like this. This has been the holy grail, not to leave any performance on the table at the end of a design," he said. "Now we feel we have a tool that will find the optimal size for transistors. And with chips coming along that have a hundred million transistors or more, who is going to be able to do this any other way?"