Low-k dielectric materials are one of the key enablers to propel Moore's Law. But in general, the low-k market has been stalled and pushed out, due to the complexity and confusion among the various technologies in the market.
The problems have also caused many chip makers to go with fluorine-doped silicate glass (FSG) as the insulating material of choice--instead of lower k products. And recently, the 2001 International Technology Roadmap for Semiconductors (ITRS) "decelerated" the pace for low-k dielectrics in future chip designs.
To get a handle on the problems and outlook for low-k, SBN talked to Mark McClear, business director of advanced electronic materials at Dow Chemical Co. of Midland, Mich. Dow claims to be the only low-k provider in production. IBM, Fujitsu, and Sony are using Dow's SiLK spin-on materials in their respective chip designs.
SBN: What are the barriers of deploying low-k and when will it enter mainstream chip production?
McClear: The integration of low-k dielectrics has been a huge challenge, making low-k adoption tougher than we at Dow or anyone in the industry ever imagined. Why? First, low-k dielectrics represent a fundamental materials change for chip manufacturers--SiO2 has been the industry's standard insulating material for more than four decades. Second, unlike most process materials, low-k dielectrics remain with the device forever. This means they must be compatible with every back-end-of-line manufacturing step through test, assembly and packaging, and must not impinge long-term device reliability.
The good news is that the majority of the integration challenges encountered in the early stages of low-k adoption (i.e., cleaning, CMP, etch and adhesion) have been solved. The industry's focus has now moved on to more advanced integration issues, such as optimizing design rules for reliability, production yield, and back-end packaging.
In spite of these challenges, low-k materials are beginning to enter mainstream production. Dow's SiLK semiconductor dielectric resin was the first true low-k material to be used in production in the 130-nm technology node at a leading chip manufacturer. Based on the latest ITRS targets, we anticipate broad-based low-k materials adoption to take hold beginning in the 90-nm technology node.
SBN: Can you comment on reports that IBM is having a difficult time getting Dow's SiLK low-k materials into production at 130-nm?
McClear: All customers who have tried to implement low-k dielectrics (CVD or spin-on) have faced integration challenges-- the key differentiator is whether those integration issues can be resolved. We feel that IBM's recent announcement that they have extended SiLK to their 90-nm technology is an affirmation of both this as well as their SiLK strategy.
SBN: What advantages do lower k materials have over FSG?
McClear: Given the low-k integration challenges mentioned above, FSG became a stopgap dielectric for a large part of the industry in the 130-nm technology node. According to definitions outlined in the 2001 ITRS, FSG isn't a low-k material at all because its k-value of >3.6 is far too high.
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Dow's SiLK resin (k=2.6) was the first low-k material in production at the 130-nm technology node. However, those suppliers that chose FSG in the 130-nm technology node will need to move to true low-k materials for the 90-nm node to stay competitive.
SBN: The 2001 ITRS roadmap "decelerated" the pace for low-k dielectrics. Can you comment on the matter?
McClear: It's important to remember that device performance is influenced by the effective k value of the entire dielectric stack--that is, the combined k-value of the bulk low-k material and the dielectric constant of the etch stop, barrier layer and hardmask films that make up the dielectric stack. The 2001 ITRS update reflects this important distinction and is also more realistic in terms of what effective k value is achievable and when the new materials will be ready to be implemented in production.
Due to this change, the industry's focus is now expanding beyond bulk low-k materials to include discussions about what the finished dielectric stack looks like, whether it provides true low-k capability, and what its cost of ownership is.
SBN: At present, there is a perception that CVD has more momentum over spin-on in terms of low-k deployments in the market. ASMI, Applied, Novellus, and others are perceived to have the lead over Dow and the other spin-on providers. Is this true or not?
McClear: Unfortunately, low-k discussions have been clouded by misinformation and market hype. This is understandable--every prospective low-k supplier has a stake in the low-k market (estimated to grow to $400 million in the next few years). Change will not be easy, especially for those suppliers that have built billion-dollar tool businesses based on the paradigm of depositing CVD films under vacuum.
More importantly, it is generally accepted that spin-on low-k offers the clearest path to future technology nodes, mainly because it's the only technology that has been shown to be extendible to below k=2.0. While CVD technology suppliers have made incremental progress in low-k film development, they'll need to overcome major technology hurdles in each new device generation if they are to deliver the yields and reliability that are prerequisites for full-blown production at major IC companies.
SBN: Besides IBM, what chipmakers are deploying Dow's SiLK low-k technology and what does it bring to the party?
McClear: It is not our place to cite specific customer names, but we can say that three major IC companies are in production with SiLK resin at 130-nm, and other than some next-generation technology announcements and marketing hype, no CVD low-k supplier can claim this.
With a k-value of 2.6, SiLK resin gives chipmakers the device performance benefits of low-k today, with a clear extendibility path tomorrow. Because we've developed the entire family of SiLK resins for ease of integration across multiple generations, the investments in learning and toolsets for the 130-nm node can be leveraged through the 45-nm generation. This means that IDMs and foundries can leverage proven integration schemes and materials that are available today (SiLK and porous SiLK resins, and Ensemble films) across multiple process generations without having to develop radically different integration knowledge.
SBN: What is Dow's low-k roadmap at 90-nm and beyond?
McClear: Dow's low-k roadmap extends through the 45-nm technology node, and is aimed at addressing the performance requirements of the entire integrated dielectric stack. By employing conventional integration schemes and a common materials deposition toolset, chipmakers can use combinations of SiLK resin (k=2.6), porous SiLK resin (k=2.1) and ENSEMBLE dielectric solutions (spin-on thin films (k=2.9) for the etch stop, hardmask and barrier layers) to stay ahead of the ITRS for the next four generations.
SBN: What is the SiLK alliance and what does it bring to the party?
McClear: Dow identified low-k integration issues as a major barrier to low-k materials adoption very early in the development of the low-k market. We spearheaded the formation of the SiLKnet Alliance in response to this need.
The SiLKnet Alliance is the industry's first and broadest collaboration on low-k materials integration. Since the Alliance was founded with nine charter members at Semicon West last year, membership has grown to more than 20 equipment and materials companies, representing every major processing module. These companies are developing a variety of fab-ready products and processes that are compatible with SiLK resins and ENSEMBLE dielectric solutions for the integrated stack.
We encourage you to take a look at the SiLKnet Alliance Web site (www.SiLKnetAlliance.com), where you'll find the latest information about the Alliance's activities, as well as links to member companies.