SAN FRANCISCO Chip designers planning to scale their system-on-chip designs to the 65-nanometer process technology node by the middle of the decade were given fair warning at Semicon West this past week: Steering past delays in lithography, interconnects and other elements crucial to extending Moore's Law will require some tricky navigation.
Designers may need to rely heavily on more expensive phase-shift masks and other enhancement techniques, at least until a somewhat delayed 157-nm lithography solution arrives. Similarly, problems with porous low-dielectric-constant (low-k) materials may force chip designers to add repeaters to global interconnects. And challenges in bringing on a high-k gate insulator could bedevil designers worried about current leakage and reliability.
Dean Freeman, an equipment analyst with Gartner Dataquest, said he is most concerned about whether a high-k replacement for silicon dioxide will be ready in time. But "history shows that when backed into a corner, the industry always manages to find a breakthrough," he said.
Although 193-nm photoresists remain immature for example, they cause some line-and-space patterns to crumble or collapse lithography is finally moving this year to 193-nm scanners. That will support the industry's move through the 90-nm technology node, which leading-edge semiconductor manufacturers are readying for mass-production next year.
For the 65-nm node, 193-nm scanners can be used for most layers of a design without resorting to "hard" phase-shift masks, which can cost two or three times as much as binary masks. But for the first four critical layers isolation, gate, contact and first-metal pattern formation access to 157-nm lithography is needed.
Most problematic may be developing a 157-nm photoresist. Asahi Chemical Corp. (Tokyo) recently reported promising results with its 157-nm resist program, but skeptics doubt commercial-grade 157-nm resists can be readied in the next two or three years.
Tony Yen, co-director of the lithography program at International Sematech (Austin, Texas), updated Sematech's progress report on 157-nm lithography at a breakfast seminar organized by FSI International Corp. (Chaska, Minn.). "For the early phase of the 65-nm node, we might see relaxed design rules. We might have to live with 193-nm lithography for a while, even though the mask error factor will be tight," Yen said. "Only with 157-nm lithography will we enjoy the same k1 factor as we have had with the 130-nm and 90-nm nodes."
The k1 factor refers to a combination of reticle enhancement techniques including phase-shift masks, optical proximity correction and other methods to deliver a comfortable process latitude. But those tricks add to the cost of the mask set and thus pose an increasingly high barrier to a wide swath of the semiconductor design community.
If 193-nm lithography is used for 65-nm designs, with a heavy reliance on phase-shift masks for the critical layers, some fear the cost of a full mask set could soar to $2 million in cases where several hard masks are required.
"We need 157-nm lithography to carry the 65-nm node," said Yen, who is assigned to Sematech from Taiwan Semiconductor Manufacturing Co. "The 65-nm generation will start at the beginning of 2005, but we think that 157-nm lithography will not quite be ready then; it will hit toward the end of '05. So the industry may have to use 193-nm tools with 0.85-NA numerical-aperture lenses, with somewhat relaxed design rules, until the full 157-nm solution is ready."
While 157-nm lithography is an optical approach, it requires a basic lens material of a higher quality than is currently available, said Phil Ware, a senior fellow at Canon Inc.'s lithography division. Calcium fluoride is used in very limited quantities for the lenses employed in the 193-nm scanners coming to market now, he noted, but 157-nm lenses will require a higher-quality crystal.
"Many people don't quite understand that the technical challenges facing us are exponentially more difficult than what we have faced thus far," Ware said.
Interconnects are in the same boat. The low-k insulators needed for the 65-nm node probably won't be ready to meet the timetable put forth by the International Technology Roadmap for Semiconductors (ITRS). Again, designers may have to design around the problem.
Current low-k materials, with a k-value of 2.6 or higher, have had a decidedly mixed yield history, forcing most companies to delay the shift from fluorinated silicate glass. Hunter Martinez, a Motorola researcher assigned to Sematech, said the road map for the 65-nm node calls for a k-value of about 2.4 and not for the dielectric material itself, but for the entire multilayer stack that makes up the intermetal layers. That requires a dielectric material with an inherent k-value of around 2.2.
That, in turn, will require the use of porous materials that, when dried, polymerize to leave a network of open space. In effect, air will enable the low k, and the polymer will keep the mechanical structure intact.
"The problem is that these materials are essentially sponges," said Martinez. "They are hard to clean, they absorb chemicals from other process steps and then they contaminate other materials."
At a Sematech-organized seminar on advanced interconnects, Alain Cannizzaro of STMicroelectronics said both the modulus and the adhesion of the new materials are substantially inferior to the characteristics of existing materials. When subjected to the stresses of chemical-mechanical polishing, thermal and cleaning steps, the materials may tear apart or separate from the metal. Since they are porous and relatively soft, they may absorb chemicals. The most pernicious result is that they tend to let captured ammonia leach out through vias, contaminating photoresists and plugging vias with undeveloped resist.
The squishiness may severely limit the chemical-mechanical polishing speed and pressure or even make the step altogether impossible. Even switching to non-abrasive polishes doesn't solve the problem completely. The mechanical weakness of the material also causes problems downstream, in wire bonding and solder bump connection.
Researchers said they expect the problems to be solved but acknowledged that the industry is running behind. "We are already late in developing the materials called for in 2004 on the ITRS road map," warned Brian Daniels of Honeywell Electronic Materials. The challenge, he said, is forming a material that is just porous enough to achieve the necessary dielectric constant and then learning to treat the material with sufficient care.
That's where the chip design team comes in, Daniels said. In the end it is the designers, not the ITRS, who determine the necessary dielectric constant.
"People are learning to design around a higher k by being smart about distances of closest approach in their metal designs," Daniels said. Improved routing algorithms could keep metal runs farther apart particularly in the lateral spacing, where most of the intermetal capacitance is generated making the design less sensitive to k. By taking such pains in the design process, a team might eliminate some delicate mask-and-etch operations, enable the use of simpler materials and do away with serious failure modes. In short, it could get higher yields.
"Chip design must be part of the integration team," Daniels said. "Otherwise you have to be much more aggressive in your process." Integrated device manufacturers may have a natural advantage in that regard, he noted, since their chip design, process and manufacturing people are all under one roof.
But the situation presents a serious problem for foundries: Having no control over how carefully their customers design for k tolerance, foundries must push their processes at least to the ITRS benchmark numbers, in order to make processes robust enough to take everything the customers throw at them.
The industry faces even bigger issues with high-k gate insulators. Because of quantum-effect tunneling through 15-angstrom gate insulators made with oxynitride, the industry is desperate for a new gate insulator. Hafnium-based materials and other candidates are being tested, but they may require a shift to atomic-layer deposition (ALD). Analyst Ron Leckie of research firm Infrastructure said a survey of 120 experts at an Electro-chemistry Society symposium in May showed a split, with half believing ALD will be used for high-k deposition and nearly the same number backing metal-organic chemical-vapor deposition.
And the industry is far from agreeing on which high-k material is best able to reduce current leakage without cutting carrier mobility through the channel. "At the beginning of this year, I was astounded to see the renewal of the ITRS road map listing 20 gate materials," said Thomas Seidel, chief technology officer with thin-film deposition vendor Genus Inc. Equipment makers cannot tolerate investigating so many chemistries, he said.
Dataquest's Freeman acknowledged that power dissipation problems are among the most critical facing the semiconductor industry but added that new high-k materials may not be ready in time for the 65-nm node. "The gate is difficult. It may get pushed back to the 45-nm node," Freeman said.
Additional reporting by Peter Clarke, news director for Semiconductor Business News.