SAN MATEO, Calif. Yield and reliability issues threaten the touted dual-damascene copper interconnect structures of leading 130-nanometer processes, having caused both poor yields at wafer sort and unacceptable failure rates over the life of apparently good chips, according to a wide range of industry sources.
Some of the mechanisms leading to those problems can be controlled by an unprecedented level of attention to processing steps, and leading foundries have demonstrated such devotion to detail in recent months. But other problems are inherent in the structure of the new interconnect stacks and can be addressed only by design rule changes and by changes in design practice, some reaching clear back to the architectural levels of design.
Thus, what first appeared in mid-2001 to be a detailed process issue has become an architectural consideration for chip design teams.
The failures involve vias between metal layers in the interconnect stack. The failures are specific to dual-damascene copper metal stacks, and the issues involved appear to affect all current processes, though foundry response to the problems has reportedly varied by vendor.
Signs of mortality
Early in the progress of 130-nm production, it was observed that some vias even though they appeared to be correctly imaged and formed were not connected or presented such a high resistance that they had a major electrical impact on the circuit. Later, it was discovered that those effects could appear during accelerated life testing in chips that had shown neither initial defects nor to the concern of reliability engineers infant mortality.
"In some cases we were still seeing new failures after 300 hours of stress testing," reported one insider at a fabless vendor.
It was necessary to identify the failure modes and correct the problem before declaring 130-nm processes fully production-ready. Yet the lack of surface defects the usual cause of circuit failures in ICs or of visible surface abnormalities concerned process integration engineers.
The problem turned out to be a confluence of several failure mechanisms, according to Bob Havemann, vice president of technology, process integration and applications at Novellus Systems Inc. "It's ironic that copper was ballyhooed for its superior reliability in IC interconnect," Havemann observed. "It can in fact be highly reliable, and it's not as subject to some of aluminum's problems, but you absolutely have to do the process right."
At least three mechanisms exist for via failure, Havemann said. Two start with one or more small voids in the metallic copper that forms the via. Through either electromigration or more critically thermal-stress migration, the voids can join, migrate to the bottom of the via and open the connection between the via and the barrier over the underlying metal layer. The third mechanism also involves thermal stress, but here the stresses are so great that the via metal physically tears away from the barrier, forming a void.
Avoiding the first two mechanisms is a matter of being meticulous in every process step in the interconnect stack, Havemann said. But to illustrate the complexity of the issue, he listed some of the process steps involved. "After patterning the trench and after the ash step to remove resist, and again after etch to remove the silicon nitride barrier, you have to be extremely careful to remove any possible leftover material from the walls and bottom of the via hole. The walls of the hole must be absolutely vertical to prevent void nuclei from forming.
"There are further steps, including a sputter etch to remove the oxide at the bottom of the hole, that must again be watched for possible contamination. When the copper seed is placed in the bottom of the hole, you have to be careful not to let the top of the trench begin to pinch off. Anything that leads to a suboptimal structure in the hole has the potential to form voids."
Unfortunately, Havemann warned, the operating temperature of fast, dense CMOS chips is almost ideal for promoting the growth and migration of voids in copper. So both thermal cycling during processing and thermal cycling from normal operation can cause the gradual joining and migration of voids.
Even if the mechanisms of void formation are successfully stopped, a failure mode remains that is not inherently a process issue. Rather, it is associated with the mechanical properties of copper.
As a segment of copper interconnect is heated, it begins to expand. Since the copper is constrained by its trench, it compresses. But beyond about 200°C, the metal moves out of its compressive phase and enters a region of plastic flow, relieving the compressive stresses. When the metal is cooled again to below its stress yield point, it begins to contract, and high tensile stresses build up. In wide segments of copper, the metal has been observed to develop enough internal tension during cooling to simply rip the via roots off the barrier layer on the underlying metal.
Since this thermal cycle lies within the range of temperatures used in wafer processing and can also occur in both accelerated life tests and normal operation on some chips, the mechanism becomes a major issue. It occurs primarily in upper layers of the metal stack where copper traces are widest.
There are several strategies for coping with this mechanism. One being explored by some process integration engineers is to add a dopant to the copper to increase its stress yield point (the point at which the metal becomes plastic), bringing it nearer to 450°C.
But the current approach appears to be much more brute-force to encourage design teams not to place isolated vias under wide areas of metal. That can be achieved either by separating a wide metal run into several narrower strips in the immediate area of a via or by placing multiple redundant vias under wider chunks of copper.
Such "encouragement" has been incorporated into design rules for some 130-nm processes. "We made a change to the design rules, requiring redundant vias in some circumstances," reported a spokesperson for Taiwan Semiconductor Manufacturing Co. "This was done last November, and our partners are fully aware of it. . . . We anticipate that the rule will remain in effect for our 130-nm and 90-nm processes."
A design manager at a fabless IC company reported that IBM Microelectronics had also made adjustments to design rules encouraging the use of redundant vias in some metal configurations.
All of the sources stated that the design rule adjustments appear to have eliminated the problem. But the redundant vias provide some interesting questions for design teams.
Should designs be laid out to avoid vias under large areas of metal? If redundant vias are used, can circuit analysis count on all of the vias' remaining intact, or should the circuits be analyzed with various numbers of vias conducting? This is a particularly important question for both timing estimation and analysis of analog circuits.
In any case, test strategy should be adjusted to look not just for open circuits but for any unexpectedly high resistance. This could indicate a failed via or the existence of voids near the bottom of the via hole.
But Havemann expressed skepticism about early detection, maintaining that there is no substitute for the tightest control over process steps. "Even if you have the process nailed down, things can go out of whack from day to day. You have to keep monitoring the vias," he said. "Unfortunately, there is no easy way to do that.
"Resistance measurements usually won't be sensitive enough to tell you about voids that aren't at the bottom of the via yet. Even looking at via chain yield on test chips where thousands of vias are strung together in huge chains won't show poor adhesion that will result in thermal stress separation.
"We use a voltage contrast microscope to examine vias, so we can actually see the voids. But that may not be practical as a process control. The key is to do everything you can to optimize adhesion."
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