ROCHESTER, N.Y. Keynote speakers at the 15th IEEE ASIC/SoC conference here today (Sept. 25) described similar challenges, and some strikingly different solutions, to moving system-level IC designs to the 90-nanometer process node. Both speakers foresee a fundamental role for embedded DRAM and a growing importance for embedded field-programmable logic.
Hirokazu Hashimoto, chairman of NEC Electronics Inc., led off the conference's plenary session by emphasizing the diversity of technologies needed to exploit the 90-nm process node. Users' needs are diverging into three separate sets, he said: network/server needs driven by the requirement for 10-GHz performance; mobile device needs characterized by the mandate for power efficiency; and a consumer market driven by time-to-market forces.
In addition to familiar process and tool issues, Hashimoto cited embedded DRAM as a key tool for high-speed system-on-chip (SoC) design. He briefly described NEC's thinking on advanced metal-insulator-metal DRAM cells to provide high performance. He also said that novel design techniques, including the conversion of static circuits to domino logic and eventually the use of self-timed logic, will be necessary.
For the consumer market, Hashimoto proposed the use of dynamically reconfigurable logic in SoCs to solve the time-to-market problem. He said that NEC had implemented a reconfigurable device, configured directly from C-language tools, that had successfully implemented an AEC encryption engine with results comparable to an ASIC design, and significantly faster than a conventional FPGA.
Hashimoto also said that reconfigurable logic could help overcome the growing non-recurring engineering charges associated with ASIC designs. He said that application-directed gate arrays with some complex embedded blocks would also be important.
The session's second speaker, Tom Bednar, senior member of the technical staff at IBM Microelectronics, said he agreed with much of what Hashimoto had said. But he differed significantly in two areas. Bednar said he sees embedded FPGA functions being used primarily for design-time flexibility rather than as field-reconfigurable elements. Bednar pointed out joint development work with Xilinx Inc. that will put 10-k, 20-k and 40-k-gate embedded FPGA blocks into IBM's ASIC library.
Bednar also differed from Hashimoto on embedded DRAM. At the 90-nm node, the IBM engineer said, the added cost of the eDRAM process would often be more than compensated by the reduction in high-speed I/O required on the SoC if critical memory were on-chip. He foresaw eDRAM content of up to 200 Mbits being economical in the 90-nm process.
IBM will use an enhanced deep-trench DRAM process, Bednar said. The technique moves all major thermal-cycle process steps before any of the logic fabrication steps, so fabricating the DRAM trenches wouldn't impact the logic's thermal budget, Bednar said. Further, the trench structures could be sufficiently planarized so as not to interfere with IBM's elaborate copper metal stack. DRAM would be available in either speed or density optimizations and would be tilable at 90 nm, he said.
Both speakers agreed on the importance of controlling power. Bednar described an approach that allows multiple islands of different voltages on a die, sometimes using on-chip regulators or distributed transistors to dynamically alter operating voltage for particular blocks.
Bednar also said that multiple oxide thicknesses would be used, and that by 65 nm novel transistor structures, possibly FinFETs or other dual-gate devices and possibly strained silicon, would replace today's MOSFETs.