The 48th International Electron Devices Meeting, planned for Dec. 8-11 in San Francisco, may signal some new directions in semiconductors, as the industry shifts to a "postplanar" era of FinFETs and other double-gate devices and goes beyond bulk silicon to fully depleted silicon-on-insulator and strained-silicon technologies.
The IEDM schedule includes a Grove-on-Moore luncheon speech, as Intel Corp. chairman Andrew S. Grove speaks on the "changing vectors of Moore's Law." Is Intel founder Gordon Moore's once-revised prediction about transistor growth due for another slowdown, coming this time from Grove? The answer, of course, must wait until December.
What is clear from the IEDM abstracts or one-page summaries of the full papers is that it's not your mother's CMOS anymore, not at Grove's Intel, not at IBM and perhaps not anywhere in the not-too-distant future.
As an indicator, Intel will present two papers, dealing with integrated circuits and manufacturing, in the opening papers session that demonstrate the point.
One of them describes Intel's 90-nanometer logic technology, which uses a graded silicon germanium layer in the channel to strain the active layer of silicon on top. The abstract promises that "several techniques with various germanium concentrations have been evaluated and will be presented."
Intel's second paper in the session describes an equally important divergence: The company will add SiGe bipolar transistors to the strained-silicon logic technology, creating a 90-nm process aimed at communications markets. The SiGe heterogeneous bipolar transistors operate at 100 GHz, with a cutoff frequency of 150 GHz. The 90-nm technology supports CMOS RF devices, metal-in-metal capacitors and other passive components required to fully integrate the RF and digital functions of a cell phone onto a single chip.
Intel has used the process to make a 10-Gbit/second serializer/deserializer "certification" vehicle as a way "to comprehend the high-frequency risks of the technology," according to the abstract.
The 2002 IEDM features at least 10 papers with strained silicon as a major theme. A group of Massachusetts Institute of Technology researchers, including strained-silicon pioneer Judy Hoyt and fellow MIT professor Dmitri Antoniadis, will deliver an overview of the research community's work on strained silicon.
Enhancing the mobility of the holes in the PFETs has been more difficult than electron-mobility enhancement in NFETs made with a strained-silicon process. The MIT researchers will review the prospects for a novel, promising technique that sharply increases the amount of germanium in the PMOS transistors by inserting a thin, high-germanium-content layer of strained SiGe below the strained-silicon layer.
Toshiba Corp. researchers, meanwhile, will show just how much can be accomplished by scaling silicon to 65-nm dimensions. The gate length in the Toshiba 65-nm bulk CMOS technology is 30 nm, with an SRAM cell size of 0.6 microm2 and an embedded-DRAM cell size of 0.11 microm2.
IBM Corp. researchers will go to IEDM will a slew of papers. One describes the smallest MOSFETs reported to date, with 4-nm silicon channels and 6-nm gate lengths. Using conventional CMOS process technology on bonded SOI wafers and halo implants to avoid the short-channel effect, the IBM team employed 248-nm-wavelength lithography to create the ultrasmall devices, which they call XFETs, for "extremely small field-effect transistors."
While IBM's work may prove that conventional MOSFETs can be scaled, many believe such small-gate-length devices will be more difficult to fabricate and control than double-gate-length devices. The FinFET, first developed at the University of California at Berkeley, has emerged as this category's leading candidate. Made with a tall, thin (finlike) channel with gates on each side of the "fin," FinFETs will be in the spotlight at IEDM.
Advanced Micro Devices Inc. researchers have made FinFETs with 10-nm gate lengths on bonded SOI wafers, using a process that is only slightly modified from a conventional CMOS flow. To achieve good performance and greatly improved power dissipation, the width of the fin which is equivalent to the body thickness in a planar CMOS device must shrink. The AMD paper will describe an aggressive pattern-reduction technique to produce narrow fin widths and gate lengths in the 10-nm range.
IBM is taking its FinFETs to IEDM as well, describing for the first time fully functional FinFET SRAM memory cells. While inverter logic circuits based on FinFET transistors have been demonstrated, the IBM paper advances FinFET integration by creating SRAM cells that are comparable in density to standard planar CMOS SRAMs built with 180-nm (0.18-micron) design rules. The IBM team developed a design-automation tool to convert conventional designs to FinFET designs significant because FinFET layout is said to be difficult.
Another IBM paper describes double-gated FinFETs and fully depleted SOI devices created with metal-gate electrodes, rather than the depletion-prone polysilicon-gate electrodes used in planar CMOS gates today. The IBM technology achieves devices with the correct threshold voltage by using silicides with the appropriate work function, rather than by body or halo doping.
IBM claims it is first out of the chute with double-gate devices incorporating metal gates, with performance metrics that match or beat planar CMOS devices.
Taiwan Semiconductor Manufacturing Co., which counts former Berkeley professor and FinFET pioneer Chenming Hu as its chief technology officer, will introduce the Omega FET, with a gate shaped like the Greek letter *. TSMC's Fu-Liang Yang will describe an omega-shaped device with a "conservative" gate oxide thickness of 17 to 19 angstroms, according to the paper's abstract.
TSMC has created Omega FETs operating at 1 volt and a low-power version running at 0.7 V. The 1-V transistors delivered drive currents of 1,440 microamperes per micron for the NFETs and 780 microA/microm for the PFETs, with very low leakage current levels in the "off" state. The gate delays are better than the performance projections called for in 25-nm-gate-length devices by the International Technology Roadmap for Semiconductors.
Believe your eyes and ears
This year's IEDM includes a session on medical applications, including advances in applying electronics to the human senses of sight and hearing, and an "electronic nose" that can be used for security systems, land mine detection and disease diagnostics.
Nathan Lewis, a professor of chemistry at the California Institute of Technology, built a chip with an array of polymeric sensors that is able to detect different vapors according to their chemical compositions, down to low parts-per-billion concentrations. Pattern-recognition algorithms are used to identify the odors, much in the way that mammalian olfactory sensors produce diagnostic patterns and transmit them to the brain for processing and analysis. The approach has "targeted national security applications," according to the Cal Tech paper abstract.
Help for macular degeneration
A paper from Oak Ridge National Laboratory and the University of Tennessee at Knoxville, along with the Doheny Eye Institute at UCLA, describes attempts to insert photoactive agents into retinal cells for people with age-related macular degeneration and other diseases of the eye.
The team will describe ways to help people who lack photoreceptor activity, though the neural wiring from the brain to the eye remains intact. The photoactive agents are plant proteins, or membrane pigment-protein complexes, making the effort among the first to attempt to implant plant proteins into mammalian cells.
Kensall Wise, a University of Michigan professor who has pioneered bioelectronics for the past three decades, will go to San Francisco to describe a MEMS-based ear implant. Wise will describe a cochlear prosthesis based on a thin-film electrode array that may help the profoundly deaf.
The three days of papers will be preceded by short courses on Sunday, Dec. 8, on RF devices and the future of CMOS manufacturing, featuring speakers drawn from both academia and industry. The committee accepted 212 papers from 598 submitted abstracts. Tuesday evening rump sessions on Dec. 10 will look at two questions: "Will SOI ever become a mainstream technology?" and "Embedded memories: What makes sense, cents?"
The IEDM Web site has registration information and more details about the agenda. Launched in 1954, IEDM is organized by the IEEE's Electron Devices Society.