MANHASSET, N.Y. Agere Systems Inc. announced today (Oct. 21) that it is shipping an 80-Gbit/second switching processor that performs per-channel rate grooming for multiservice switching of voice and data signals. The chip performs three jobs serializer/deserializer functions; clock-data-recovery functions, and packet processing and can reduce the cost of network switching by up to 70 percent, Agere said.
ZTE Corp. of China will use the chip in its equipment, Agere said.
The PI-40SAX Protocol Independent standalone switch can switch up to 320,000 voice and data calls, or "eight times that of the industry's state-of-the-art Class 5 switches, such as the 5ESS from Lucent," said Wei Li, systems architect for infrastructure products at Agere. The aggregate 80-Gbits/s switching speed guarantees 40-Gbit/s bandwidth rates, or four times as much as other current solutions, Agere said. The chip has thirty-two 2.5-Gbit fabric ports, each of which can be assigned or aggregated to Gigabit Ethernet, OC-12c, OC-48c or OC-192c rates.
Instead of a bit-slicing approach, the PI-40SAX uses a shared-memory architecture plus a platform-based approach that allows for real-time scheduling and rate grooming on a channel-by-channel basis, Wei said.
"Bit slicing gives a master/slave configuration, which leads to poor reliability as any one link can bring the system down," said Wei. "A shared memory overcomes this."
For rate-grooming and traffic management, Agere worked on algorithms for real-time per-channel bandwidth provisioning for voice-over-Internet Protocol, which helped preserve quality-of-service and service-level-agreements. Traffic isolation and separate buffer pools for unicast and multicast data are also included. The switch handles time-division multiplex, asynchronous transfer mode and IP traffic with equal aplomb.
Agere had to develop a low-power serializer/deserializer to implement the single-chip solution, however, said John Sotir, product marketing manager at Agere. The integration of the serdes was made possible by dropping that function's power consumption at 2.5 Gbits/s to 85 mW, "versus the 125 mW typically required by current solutions," said Sotir. Agere's own first-generation serdes sucked 200 mW, he said.
The PI-40SAX is implemented in a 0.16-micron process and is priced at $520 each per 10,000. It is the third member of the company's PI-40 chip family, which also includes the PI-40X and PI-40C multistage switching chips. The latest chip allows a customer to "collapse its multiservice networks down to a one-chip architecture and platform for current and future requirements," Sotir said.