SAN JOSE, Calif. Advanced Micro Devices Inc. said its upcoming Opteron microprocessor will feature better integer performance than all other server processors, setting up a possible race with Intel Corp. to move to dual-core server processors as early as next year.
AMD's 64-bit X86 processor running at 2 GHz in a 32-bit mode will hit an estimated SPECint base2000 performance rating of 1,202 and a SPECfp base2000 rating of 1,170, said Fred Weber, chief technology officer of AMD's computation products group, at the Microprocessor Forum here Tuesday (Oct 15).
The closest competitor, Intel's 2.5-GHz Pentium 4 Xeon processor, sports an integer performance rating of 893, followed by the Intel's Itanium 2 with a 810 rating and IBM Microelectronics' dual-core Power 4 at 790.
"That's very impressive performance," said Nathan Brookwood, an analyst with Insight64 (Saratoga, Calif.). "It beats everything else out there in integer performance, though they are still behind Intel's Itanium in floating-point performance."
The numbers presented by AMD are based on unverified tests performed at the company's labs, presumably on its high-end Sledgehammer processor. AMD said the benchmark was run on a chip with 1 Mbyte of internal cache and external PC2700 DDR main memory using existing Intel X86 compilers.
Weber showed charts indicating the Opteron benchmark performance will scale more dramatically than for Intel's Xeon as both processors ratchet up their frequency. In addition, he predicted that AMD would announce in about five months a further 10 percent to 20 percent performance increase for the processor in its 64-bit mode.
"This really validates AMD's story that you don't have to go to a new architecture like Intel's Itanium to get 64-bit performance. You get 64-bit addressing without sacrificing 32-bit performance," said Kevin Krewell, senior analyst with the Microprocessor Report.
Speculation quickly turned to when AMD or Intel will move to dual-core processors as their performance race heats up. Both companies have said such a move becomes viable with 90-nanometer process technology, but neither company was willing to discuss any product plans.
Intel will deliver a 90-nm version of its Xeon dubbed Nocona in 2003. However, Robert Yung, chief technology officer for Intel's enterprise processor group, would not say if that will be a dual-core part.
"My biggest fear is they will do that," said AMD's Weber.
For its part, AMD said it has tested the Opteron RTL design at the logical level for a dual-core configuration and said that approach would be feasible at 90 nm. It also said it plans to apply a 90-nm process to a derivative of Opteron in late 2003.
"Dual core is a lot of work for an unclear ROI," said Weber. While a dual-core part could boost performance by as much as 80 percent, it would also have a significant impact on power consumption as well as cost and time-to-market, he added.
Analyst Krewell said Intel would get a bigger performance bang by adding dual-core support to its high-end Itanium processor since that device is usually designed into systems with four or more processors.
AMD's Weber was cool on simultaneous multithreading, a technology Intel has already added to its Xeon processors.
"I think Intel is doing it backwards," he said. "You need to start with on-chip multiprocessing, then go to multithreading to get the full benefits. With multithreading you are sharing the execution units the smallest part of the die but multiplying the load on the caches and registers."
AMD plans to roll out its Opteron chips in the first half of next year. Microsoft Corp. has said it will support the chips in upgrades to Windows.
Intel provided few new details on its server processor plans other than to say it will continue to increase the speed of its processor buses and the size of its Level 3 caches. "We will probably reach L3 caches beyond 10 Mbytes by the middle of the decade," said Yung.
About 88 percent of the transistors on Intel's next-generation 64-bit Itanium, called Madison, will be devoted to cache memory, or about half the chip's die area, Yung said.