SAN JOSE, Calif. Intel Corp. today (Oct. 15) described how it could combine four Itanium 2 cores that share a large cache memory to create a processor with more than 1 billion transistors.
In a keynote address here at the Microprocessor Forum, Intel fellow John Crawford said such a design is "imminently doable" from a die-size and manufacturing standpoint and that "we would expect something of this nature coming out."
Crawford did not disclose specific plans for such a processor, though he said Intel will be able to design and build a 1-billion-transistor microprocessor using 65-nanometer process technology by 2007.
Crawford went on to describe a hypothetical processor that would contain four Itanium 2 cores and 12 to 16 megabytes of shared cache memory, all connected through a leaf interconnect scheme. Each Itanium 2 processor would contain about 120 million transistors while the cache would carry 700 million to 950 million transistors, bringing the total transistor budget to well over 1 billion, he said.
Such a large cache size is desirable to overcome the slow performance of external memory, Crawford said. The leaf interconnect structure would also improve the performance of the processor cores. "Instead of over the lines, the processors could share and benefit each other," he said.
Another advantage of using a bigger cache memory is that memory cells consume less power than logic. Using four separate processor cores and spreading them around the periphery of the cache will also serve to lower power density. Crawford cited power consumption, design complexity and test and debug as the three greatest challenges to microprocessor design.
To boost the performance of the individual processor cores, Intel is looking at ways to extend its so-called Hyperthreading technology by enabling several speculative threads for a single computation.
Other technologies Intel is developing would improve the performance of managed run-time environments like Java and .Net; incorporate more hardware features to deter hacking; and slow down certain paths in a processor design with too much "slack" in order to contain chip size and power consumption, Crawford said.