The engineering of silicon into system-on-chip products will get a fair amount of attention at the upcoming International Solid-State Circuits Conference, where circuit designers will be offered a serving of SoC design methodologies. ISSCC will be held Feb. 9 - 13 at San Francisco's Marriott Hotel.
Organizers of ISSCC 2003 have arranged a special session that will repeat four presentations first made at the 39th Design Automation Conference this past June in New Orleans. One of these, by Aurangzeb Khan, corporate vice president and general manager of Cadence Design Systems Inc., describes the design methodologies and CAD-tool requirements for an advanced 10-million-gate SoC in the context of several large design examples.
Also at this year's ISSCC, a special session on circuits in emerging technologies will address emerging techniques for both high-performance design at microwave frequencies and for future gigascale integrated circuits. Some of these techniques include high-speed CMOS, silicon germanium, gallium arsenide, indium phosphide, double-gate FinFET and carbon nanotube technologies. One intriguing paper in this session, titled "Integration of Analog, Digital and Power Regulation on a Chip," will be presented by James Mielke, director of systems and architecture at Motorola (Tempe, Ariz.).
A separate evening session, titled "Analog IP Stairway to SoC Heaven?" will pose the provocative question of whether new, less ambitious paradigms can make analog electronic design automation (EDA) for SoCs a success. Panelists will include executives from Xignal; Barcelona Design; Hitachi, STMicroelectronics; Dolphin Integration; Philips Semiconductors; and a representative from Katholieke Universiteit Leuven (Belgium).
A panel session organized by K. Nagaraj of Texas Instruments Inc. looks to be controversial for silicon designers. Entitled "SoC: DOA? RIP?" it will probe how to integrate RF circuits, including high-quality passives and precision analog circuits, with ULSI digital circuitry. Issues such as noise coupling and/or MOSFET gate leakages will be contemplated as possible show stoppers for SoCs. Panelists will be from Stanford University, Texas Instruments, Motorola, Intel, Analog Devices and IMEC.