SAN FRANCISCO--During the Nanoimprint and Nanoprint Technology (NNT) conference here today, officials from Princeton University claimed to have fabricated a sub-100-nm MOSFET device on a 4-inch wafer substrate using nano-imprint lithography technology.
Nano-imprint lithography is a new and "disruptive" technology. Tools based on the technology do not utilize an optical lens, but rather it makes use of ultraviolet (UV) and liquid immersion techniques to imprint patterns on a wafer.
In a paper presented by officials from Princeton, the university said it processed a 60-nm MOSFET device with a nano-imprint tool. Using four masks and three overlay alignments, the tool demonstrated a layer-to-layer alignment accuracy of better than 500-nm, according to the paper.
"The devices are fabricated on standard p-type 4-inch silicon wafers," the paper said. "Local oxidation of silicon was used to isolate adjacent devices. Active area was doped heavily with boron to reduce the short channel effects. The gate oxide was 10-nm. The source and drain were implemented with arsenic."