SAN FRANCISCO Intel and IBM each came to the 2002 International Electron Devices Meeting (IEDM) claiming logic performance leadership at the 90-nm. But the two companies take much different technology paths: IBM uses partially depleted silicon on insulator, while Intel has adopted strained silicon technology for its 90-nm process.
And the two companies emphasize different metrics. IBM claims it has the fastest ring oscillator reported in 90-nm CMOS, while Intel, which said it does not report ring oscillator results because each company has a different method of benchmarking that circuit, claims it has the fastest drive currents seen to date for 90-nm silicon.
Intel kept much of its strained silicon recipe under wraps here, but said the results were nearly a 20 percent performance improvement, with only a few additional process steps.
Monday afternoon (Dec. 9), Scott Thompson, an Intel fellow who leads the 90-nm process development program, took the stage at IEDM to describe the "1262" process that Intel will bring to its 300-mm wafer fabs in the second half of next year, starting with the "Prescott" version P4 microprocessor.
Thompson said Intel uses an epitaxial silicon germanium to create a strain on the upper layer of active silicon, with a modest 17 percent concentration of germanium atoms.
While other companies have struggled in strained silicon to match the PMOS transistors, which use holes as carriers in the valence band, with the generally faster NMOS transistors, Thompson said Intel was able to boost the speed of its PMOS transistors at nearly the same amount as the strained silicon NMOS devices.
"In general, the industry has seen the performance of the holes roll off at high fields, but we don't see that. We accomplish that by keeping germanium out of the channel, avoiding the Coulomb effect (of electrons repelling each other)," Thompson said.
Intel will use the base 90-nm process as the foundation for a new communications process that incorporates silicon germanium bipolar transistors, integrated passives, and other communication-specific features.
Intel senior fellow Mark Bohr said with its 90-nm SiGe process, Intel is "at least one process generation ahead" of other silicon vendors vying for the communication IC market. By late 2003 or early 2004, Intel will begin making some chips on the new process, with gigabit Ethernet, optical networking, and wireless Ics among the targets.
IBM engineer Mukesh Khare presented IBM's 90-nm SOI process Tuesday morning (Dec. 10) that yields a ring oscillator circuit with measured 4.5 to 5 picosecond delays. Bohr said Intel no longer publishes a ring oscillator metric because "there is no standard way to benchmark" that circuit.
Ghavam Shahidi, an IBM fellow, said IBM's "worst case off current is a lot less than Intel's," because the use of an SOI substrate allows "a much gentler I(subscript)off(end subscript) curve" than does bulk silicon.
Ironically, IBM has been a leading proponent of strained silicon, with numerous papers published at IEDM and elsewhere over the last five years. But Intel will take strained silicon to market earlier than IBM and others. In a late paper planned for late Tuesday, IBM will describe its plan to marry strained silicon with SOI at the 65-nm node.
Thompson said Intel believes it can get another performance boost by increasing the germanium content at the 65-nm node, without going to SOI.
Intel had been publicly negative about strained silicon, taking the industry by surprise with its adoption at the 90-nm node ahead of the rest of the industry.
Bohr said that skepticism was based on a belief that long channel strained silicon devices would see a performance degradation in the short channel devices which are needed for commercial microprocessor production. "About a year ago we saw promising results from short channel strained silicon devices and made a decision to go that way," said Bohr.